2000-06-09 16:04:30 +00:00
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/*-
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* Copyright (c) 2000 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _PCI_AGPREG_H_
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#define _PCI_AGPREG_H_
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/*
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* Offsets for various AGP configuration registers.
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*/
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#define AGP_APBASE 0x10
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#define AGP_CAPPTR 0x34
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/*
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* Offsets from the AGP Capability pointer.
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*/
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#define AGP_CAPID 0x0
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#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
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#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
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#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
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#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
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#define AGP_STATUS 0x4
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#define AGP_COMMAND 0x8
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/*
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* Config offsets for Intel AGP chipsets.
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*/
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#define AGP_INTEL_NBXCFG 0x50
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#define AGP_INTEL_ERRSTS 0x91
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#define AGP_INTEL_AGPCTRL 0xb0
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#define AGP_INTEL_APSIZE 0xb4
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#define AGP_INTEL_ATTBASE 0xb8
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/*
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* Config offsets for VIA AGP chipsets.
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*/
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#define AGP_VIA_GARTCTRL 0x80
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#define AGP_VIA_APSIZE 0x84
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#define AGP_VIA_ATTBASE 0x88
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/*
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* Config offsets for SiS AGP chipsets.
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*/
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#define AGP_SIS_ATTBASE 0x90
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#define AGP_SIS_WINCTRL 0x94
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#define AGP_SIS_TLBCTRL 0x97
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#define AGP_SIS_TLBFLUSH 0x98
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/*
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* Config offsets for Ali AGP chipsets.
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*/
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#define AGP_ALI_AGPCTRL 0xb8
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#define AGP_ALI_ATTBASE 0xbc
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#define AGP_ALI_TLBCTRL 0xc0
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/*
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* Config offsets for the AMD 751 chipset.
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*/
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#define AGP_AMD751_REGISTERS 0x14
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#define AGP_AMD751_APCTRL 0xac
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#define AGP_AMD751_MODECTRL 0xb0
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2000-06-10 17:44:53 +00:00
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#define AGP_AMD751_MODECTRL_SYNEN 0x80
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#define AGP_AMD751_MODECTRL2 0xb2
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#define AGP_AMD751_MODECTRL2_G1LM 0x01
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#define AGP_AMD751_MODECTRL2_GPDCE 0x02
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#define AGP_AMD751_MODECTRL2_NGSE 0x08
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2000-06-09 16:04:30 +00:00
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/*
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* Memory mapped register offsets for AMD 751 chipset.
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*/
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#define AGP_AMD751_CAPS 0x00
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#define AGP_AMD751_CAPS_EHI 0x0800
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#define AGP_AMD751_CAPS_P2P 0x0400
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#define AGP_AMD751_CAPS_MPC 0x0200
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#define AGP_AMD751_CAPS_VBE 0x0100
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#define AGP_AMD751_CAPS_REV 0x00ff
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#define AGP_AMD751_STATUS 0x02
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#define AGP_AMD751_STATUS_P2PS 0x0800
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#define AGP_AMD751_STATUS_GCS 0x0400
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#define AGP_AMD751_STATUS_MPS 0x0200
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#define AGP_AMD751_STATUS_VBES 0x0100
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#define AGP_AMD751_STATUS_P2PE 0x0008
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#define AGP_AMD751_STATUS_GCE 0x0004
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#define AGP_AMD751_STATUS_VBEE 0x0001
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#define AGP_AMD751_ATTBASE 0x04
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#define AGP_AMD751_TLBCTRL 0x0c
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#endif /* !_PCI_AGPREG_H_ */
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