247 lines
8.8 KiB
C
247 lines
8.8 KiB
C
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/* $NetBSD: octeonreg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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Memory Map
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0000.0000 * 128MB Typically SDRAM (on Core Board)
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0800.0000 * 256MB Typically PCI
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1800.0000 * 62MB Typically PCI
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1be0.0000 * 2MB Typically System controller's internal registers
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1c00.0000 * 32MB Typically not used
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1e00.0000 4MB Monitor Flash
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1e40.0000 12MB reserved
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1f00.0000 12MB Switches
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LEDs
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ASCII display
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Soft reset
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FPGA revision number
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CBUS UART (tty2)
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General Purpose I/O
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I2C controller
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1f10.0000 * 11MB Typically System Controller specific
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1fc0.0000 4MB Maps to Monitor Flash
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1fd0.0000 * 3MB Typically System Controller specific
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* depends on implementation of the Core Board and of software
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*/
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/*
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CPU interrupts
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NMI South Bridge or NMI button
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0 South Bridge INTR
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1 South Bridge SMI
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2 CBUS UART (tty2)
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3 COREHI (Core Card)
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4 CORELO (Core Card)
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5 Not used, driven inactive (typically CPU internal timer interrupt
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IRQ mapping (as used by YAMON)
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0 Timer South Bridge
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1 Keyboard SuperIO
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2 Reserved by South Bridge (for cascading)
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3 UART (tty1) SuperIO
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4 UART (tty0) SuperIO
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5 Not used
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6 Floppy Disk SuperIO
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7 Parallel Port SuperIO
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8 Real Time Clock South Bridge
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9 I2C bus South Bridge
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10 PCI A,B,eth PCI slot 1..4, Ethernet
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11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge)
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PCI D,USB
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12 Mouse SuperIO
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13 Reserved by South Bridge
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14 Primary IDE Primary IDE slot
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15 Secondary IDE Secondary IDE slot/Compact flash connector
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*/
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#define OCTEON_SYSTEMRAM_BASE 0x00000000 /* System RAM: */
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#define OCTEON_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
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#define OCTEON_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */
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#define OCTEON_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
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#define OCTEON_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */
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#define OCTEON_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
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#define OCTEON_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */
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#define OCTEON_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
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#define OCTEON_CORECTRL_BASE 0x1be00000 /* Core control: */
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#define OCTEON_CORECTRL_SIZE 0x00200000 /* 2 MByte */
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#define OCTEON_RESERVED_BASE1 0x1c000000 /* Reserved: */
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#define OCTEON_RESERVED_SIZE1 0x02000000 /* 32 MByte */
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#define OCTEON_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */
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#define OCTEON_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */
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#define OCTEON_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
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#define OCTEON_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */
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#define OCTEON_FILEFLASH_SIZE 0x00020000 /* 128 KByte */
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#define OCTEON_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
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#define OCTEON_RESERVED_BASE2 0x1e400000 /* Reserved: */
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#define OCTEON_RESERVED_SIZE2 0x00c00000 /* 12 MByte */
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#define OCTEON_FPGA_BASE 0x1f000000 /* FPGA: */
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#define OCTEON_FPGA_SIZE 0x00c00000 /* 12 MByte */
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#define OCTEON_NMISTATUS (OCTEON_FPGA_BASE + 0x24)
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#define OCTEON_NMI_SB 0x2 /* Pending NMI from the South Bridge */
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#define OCTEON_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */
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#define OCTEON_NMIACK (OCTEON_FPGA_BASE + 0x104)
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#define OCTEON_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */
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#define OCTEON_SWITCH (OCTEON_FPGA_BASE + 0x200)
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#define OCTEON_SWITCH_MASK 0xff /* settings of DIP switch S2 */
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#define OCTEON_STATUS (OCTEON_FPGA_BASE + 0x208)
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#define OCTEON_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */
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#define OCTEON_S54 0x08 /* switch S5-4 - set YAMON factory default mode */
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#define OCTEON_S53 0x04 /* switch S5-3 */
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#define OCTEON_BIGEND 0x02 /* switch S5-2 - big endian mode */
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#define OCTEON_JMPRS (OCTEON_FPGA_BASE + 0x210)
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#define OCTEON_JMPRS_PCICLK 0x1c /* PCI clock frequency */
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#define OCTEON_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */
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#define OCTEON_LEDBAR (OCTEON_FPGA_BASE + 0x408)
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#define OCTEON_ASCIIWORD (OCTEON_FPGA_BASE + 0x410)
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#define OCTEON_ASCII_BASE (OCTEON_FPGA_BASE + 0x418)
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#define OCTEON_ASCIIPOS0 0x00
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#define OCTEON_ASCIIPOS1 0x08
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#define OCTEON_ASCIIPOS2 0x10
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#define OCTEON_ASCIIPOS3 0x18
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#define OCTEON_ASCIIPOS4 0x20
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#define OCTEON_ASCIIPOS5 0x28
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#define OCTEON_ASCIIPOS6 0x30
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#define OCTEON_ASCIIPOS7 0x38
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#define OCTEON_SOFTRES (OCTEON_FPGA_BASE + 0x500)
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#define OCTEON_GORESET 0x42 /* write this to OCTEON_SOFTRES for board reset */
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/*
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* BRKRES is the number of milliseconds before a "break" on tty will
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* trigger a reset. A value of 0 will disable the reset.
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*/
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#define OCTEON_BRKRES (OCTEON_FPGA_BASE + 0x508)
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#define OCTEON_BRKRES_MASK 0xff
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#define OCTEON_CBUSUART 0x8001180000000800ull
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/* 16C550C UART, 8 bit registers on 8 byte boundaries */
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/* RXTX 0x00 */
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/* INTEN 0x08 */
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/* IIFIFO 0x10 */
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/* LCTRL 0x18 */
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/* MCTRL 0x20 */
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/* LSTAT 0x28 */
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/* MSTAT 0x30 */
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/* SCRATCH 0x38 */
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#define OCTEON_CBUSUART_INTR 2
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#define OCTEON_GPIO_BASE (OCTEON_FPGA_BASE + 0xa00)
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#define OCTEON_GPOUT 0x0
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#define OCTEON_GPINP 0x8
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#define OCTEON_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */
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#define OCTEON_BOOTROM_SIZE 0x00400000 /* 4 MByte */
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#define OCTEON_REVISION 0x1fc00010
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#define OCTEON_REV_FPGRV 0xff0000 /* CBUS FPGA revision */
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#define OCTEON_REV_CORID 0x00fc00 /* Core Board ID */
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#define OCTEON_REV_CORRV 0x000300 /* Core Board Revision */
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#define OCTEON_REV_PROID 0x0000f0 /* Product ID */
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#define OCTEON_REV_PRORV 0x00000f /* Product Revision */
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/* PCI definitions */
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#define OCTEON_UART0ADR 0x8001180000000800ull
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#define OCTEON_UART1ADR 0x8001180000000C00ull
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#define OCTEON_MIO_BOOT_BIST_STAT 0x80011800000000F8ull
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/**************************
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* To Delete
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*/
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#define OCTEON_SOUTHBRIDGE_INTR 0
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#define OCTEON_PCI0_IO_BASE OCTEON_PCIMEM3_BASE
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#define OCTEON_PCI0_ADDR( addr ) (OCTEON_PCI0_IO_BASE + (addr))
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#define OCTEON_RTCADR 0x70 // OCTEON_PCI_IO_ADDR8(0x70)
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#define OCTEON_RTCDAT 0x71 // OCTEON_PCI_IO_ADDR8(0x71)
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#define OCTEON_SMSC_COM1_ADR 0x3f8
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#define OCTEON_SMSC_COM2_ADR 0x2f8
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#define OCTEON_UARTT0ADR OCTEON_PCI0_ADDR(OCTEON_SMSC_COM1_ADR)
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#define OCTEON_UARTT1ADR OCTEON_SMSC_COM2_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_COM2_ADR)
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#define OCTEON_SMSC_1284_ADR 0x378
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#define OCTEON_1284ADR OCTEON_SMSC_1284_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_1284_ADR)
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#define OCTEON_SMSC_FDD_ADR 0x3f0
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#define OCTEON_FDDADR OCTEON_SMSC_FDD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_FDD_ADR)
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#define OCTEON_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */
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#define OCTEON_KYBDADR OCTEON_SMSC_KYBD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_KYBD_ADR)
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#define OCTEON_SMSC_MOUSE_ADR OCTEON_SMSC_KYBD_ADR
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#define OCTEON_MOUSEADR OCTEON_KYBDADR
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#define OCTEON_DMA_PCI_PCIBASE 0x00000000UL
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#define OCTEON_DMA_PCI_PHYSBASE 0x00000000UL
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#define OCTEON_DMA_PCI_SIZE (256 * 1024 * 1024)
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#define OCTEON_DMA_ISA_PCIBASE 0x00800000UL
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#define OCTEON_DMA_ISA_PHYSBASE 0x00000000UL
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#define OCTEON_DMA_ISA_SIZE (8 * 1024 * 1024)
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#ifndef _LOCORE
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void led_bar(uint8_t);
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void led_display_word(uint32_t);
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void led_display_str(const char *);
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void led_display_char(int, uint8_t);
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#endif
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