1993-06-12 14:58:17 +00:00
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/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)icu.s 7.2 (Berkeley) 5/21/91
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*
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* PATCHES MAGIC LEVEL PATCH THAT GOT US HERE
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* -------------------- ----- ----------------------
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* CURRENT PATCH LEVEL: 5 00167
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* -------------------- ----- ----------------------
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*
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* 28 Nov 92 Frank MacLachlan Aligned addresses and data
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* on 32bit boundaries.
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* 24 Mar 93 Rodney W. Grimes Added interrupt counters for vmstat
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* also stray and false intr counters added
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* 20 Apr 93 Bruce Evans New npx-0.5 code
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* 25 Apr 93 Bruce Evans Support new interrupt code (intr-0.1)
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* Rodney W. Grimes Reimplement above patches..
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* 17 May 93 Rodney W. Grimes Redid the interrupt counter stuff
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* moved the counters to vectors.s so
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* they are next to the name tables.
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* 04 Jun 93 Bruce Evans Fixed irq_num vs id_num for multiple
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* devices configed on the same irq with
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* respect to ipending. Restructured
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* not to use BUILD_VECTORS.
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* Rodney W. Grimes softsio1 only works if you have sio
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* serial driver, added #include sio.h
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* and #ifdef NSIO > 0 to protect it.
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*/
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/*
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* XXX - this file is now misnamed. All spls are now soft and the only thing
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* related to the hardware icu is that the bit numbering is the same in the
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* soft priority masks as in the hard ones.
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*/
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#include "sio.h"
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#define HIGHMASK 0xffff
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#define SOFTCLOCKMASK 0x8000
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.data
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.globl _cpl
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_cpl: .long 0xffff # current priority (all off)
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.globl _imen
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_imen: .long 0xffff # interrupt mask enable (all off)
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1993-06-18 02:47:24 +00:00
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/* .globl _highmask */
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1993-06-12 14:58:17 +00:00
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_highmask: .long HIGHMASK
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.globl _ttymask
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_ttymask: .long 0
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.globl _biomask
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_biomask: .long 0
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.globl _netmask
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_netmask: .long 0
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.globl _ipending
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_ipending: .long 0
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vec:
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.long vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7
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.long vec8, vec9, vec10, vec11, vec12, vec13, vec14, vec15
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#define GENSPL(name, mask, event) \
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.globl _spl/**/name ; \
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ALIGN_TEXT ; \
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_spl/**/name: ; \
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COUNT_EVENT(_intrcnt_spl, event) ; \
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movl _cpl,%eax ; \
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movl %eax,%edx ; \
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orl mask,%edx ; \
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movl %edx,_cpl ; \
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SHOW_CPL ; \
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ret
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#define FASTSPL(mask) \
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movl mask,_cpl ; \
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SHOW_CPL
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#define FASTSPL_VARMASK(varmask) \
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movl varmask,%eax ; \
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movl %eax,_cpl ; \
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SHOW_CPL
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.text
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ALIGN_TEXT
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unpend_v:
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COUNT_EVENT(_intrcnt_spl, 0)
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bsfl %eax,%eax # slow, but not worth optimizing
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btrl %eax,_ipending
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jnc unpend_v_next # some intr cleared the in-memory bit
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SHOW_IPENDING
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movl Vresume(,%eax,4),%eax
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testl %eax,%eax
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je noresume
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jmp %eax
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ALIGN_TEXT
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/*
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* XXX - must be some fastintr, need to register those too.
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*/
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noresume:
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#if NSIO > 0
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call _softsio1
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#endif
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unpend_v_next:
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movl _cpl,%eax
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movl %eax,%edx
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notl %eax
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andl _ipending,%eax
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je none_to_unpend
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jmp unpend_v
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/*
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* Handle return from interrupt after device handler finishes
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*/
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ALIGN_TEXT
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doreti:
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COUNT_EVENT(_intrcnt_spl, 1)
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addl $4,%esp # discard unit arg
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popl %eax # get previous priority
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/*
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* Now interrupt frame is a trap frame!
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*
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* XXX - setting up the interrupt frame to be almost a stack frame is mostly
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* a waste of time.
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*/
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movl %eax,_cpl
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SHOW_CPL
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movl %eax,%edx
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notl %eax
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andl _ipending,%eax
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jne unpend_v
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none_to_unpend:
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testl %edx,%edx # returning to zero priority?
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jne 1f # nope, going to non-zero priority
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movl _netisr,%eax
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testl %eax,%eax # check for softint s/traps
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jne 2f # there are some
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jmp test_resched # XXX - schedule jumps better
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COUNT_EVENT(_intrcnt_spl, 2) # XXX
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ALIGN_TEXT # XXX
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1: # XXX
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COUNT_EVENT(_intrcnt_spl, 3)
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popl %es
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popl %ds
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popal
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addl $8,%esp
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iret
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#include "../net/netisr.h"
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#define DONET(s, c, event) ; \
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.globl c ; \
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btrl $s,_netisr ; \
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jnc 1f ; \
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COUNT_EVENT(_intrcnt_spl, event) ; \
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call c ; \
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1:
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ALIGN_TEXT
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2:
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COUNT_EVENT(_intrcnt_spl, 4)
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/*
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* XXX - might need extra locking while testing reg copy of netisr, but
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* interrupt routines setting it would not cause any new problems (since we
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* don't loop, fresh bits will not be processed until the next doreti or spl0).
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*/
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testl $~((1 << NETISR_SCLK) | (1 << NETISR_AST)),%eax
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je test_ASTs # no net stuff, just temporary AST's
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FASTSPL_VARMASK(_netmask)
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DONET(NETISR_RAW, _rawintr, 5)
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#ifdef INET
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DONET(NETISR_IP, _ipintr, 6)
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#endif
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#ifdef IMP
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DONET(NETISR_IMP, _impintr, 7)
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#endif
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#ifdef NS
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DONET(NETISR_NS, _nsintr, 8)
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#endif
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FASTSPL($0)
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test_ASTs:
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btrl $NETISR_SCLK,_netisr
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jnc test_resched
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COUNT_EVENT(_intrcnt_spl, 9)
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FASTSPL($SOFTCLOCKMASK)
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/*
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* Back to an interrupt frame for a moment.
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*/
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pushl $0 # previous cpl (probably not used)
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pushl $0x7f # dummy unit number
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call _softclock
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addl $8,%esp # discard dummies
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FASTSPL($0)
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test_resched:
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#ifdef notused1
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btrl $NETISR_AST,_netisr
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jnc 2f
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#endif
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#ifdef notused2
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cmpl $0,_want_resched
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je 2f
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#endif
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cmpl $0,_astpending # XXX - put it back in netisr to
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je 2f # reduce the number of tests
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testb $SEL_RPL_MASK,TRAPF_CS_OFF(%esp)
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# to non-kernel (i.e., user)?
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je 2f # nope, leave
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COUNT_EVENT(_intrcnt_spl, 10)
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movl $0,_astpending
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call _trap
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2:
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COUNT_EVENT(_intrcnt_spl, 11)
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popl %es
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popl %ds
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popal
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addl $8,%esp
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iret
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/*
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* Interrupt priority mechanism
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* -- soft splXX masks with group mechanism (cpl)
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* -- h/w masks for currently active or unused interrupts (imen)
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* -- ipending = active interrupts currently masked by cpl
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*/
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GENSPL(bio, _biomask, 12)
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GENSPL(clock, $HIGHMASK, 13) /* splclock == splhigh ex for count */
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GENSPL(high, $HIGHMASK, 14)
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GENSPL(imp, _netmask, 15) /* splimp == splnet except for count */
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GENSPL(net, _netmask, 16)
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GENSPL(softclock, $SOFTCLOCKMASK, 17)
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GENSPL(tty, _ttymask, 18)
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.globl _splnone
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.globl _spl0
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ALIGN_TEXT
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_splnone:
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_spl0:
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COUNT_EVENT(_intrcnt_spl, 19)
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in_spl0:
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movl _cpl,%eax
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pushl %eax # save old priority
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testl $(1 << NETISR_RAW) | (1 << NETISR_IP),_netisr
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je over_net_stuff_for_spl0
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movl _netmask,%eax # mask off those network devices
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movl %eax,_cpl # set new priority
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SHOW_CPL
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/*
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* XXX - what about other net intrs?
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*/
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DONET(NETISR_RAW, _rawintr, 20)
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#ifdef INET
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DONET(NETISR_IP, _ipintr, 21)
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#endif
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over_net_stuff_for_spl0:
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movl $0,_cpl # set new priority
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SHOW_CPL
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movl _ipending,%eax
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testl %eax,%eax
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jne unpend_V
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popl %eax # return old priority
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ret
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.globl _splx
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ALIGN_TEXT
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_splx:
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COUNT_EVENT(_intrcnt_spl, 22)
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movl 4(%esp),%eax # new priority
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testl %eax,%eax
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je in_spl0 # going to "zero level" is special
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COUNT_EVENT(_intrcnt_spl, 23)
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movl _cpl,%edx # save old priority
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movl %eax,_cpl # set new priority
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SHOW_CPL
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notl %eax
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andl _ipending,%eax
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jne unpend_V_result_edx
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movl %edx,%eax # return old priority
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ret
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ALIGN_TEXT
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unpend_V_result_edx:
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pushl %edx
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unpend_V:
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COUNT_EVENT(_intrcnt_spl, 24)
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bsfl %eax,%eax
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btrl %eax,_ipending
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jnc unpend_V_next
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SHOW_IPENDING
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movl Vresume(,%eax,4),%edx
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testl %edx,%edx
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je noresumeV
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|
|
|
/*
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|
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|
* We would prefer to call the intr handler directly here but that doesn't
|
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|
|
|
* work for badly behaved handlers that want the interrupt frame. Also,
|
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|
|
* there's a problem determining the unit number. We should change the
|
|
|
|
|
* interface so that the unit number is not determined at config time.
|
|
|
|
|
*/
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|
|
jmp *vec(,%eax,4)
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|
|
ALIGN_TEXT
|
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|
|
|
/*
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|
|
|
|
* XXX - must be some fastintr, need to register those too.
|
|
|
|
|
*/
|
|
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|
|
noresumeV:
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|
|
|
#if NSIO > 0
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|
|
|
call _softsio1
|
|
|
|
|
#endif
|
|
|
|
|
unpend_V_next:
|
|
|
|
|
movl _cpl,%eax
|
|
|
|
|
notl %eax
|
|
|
|
|
andl _ipending,%eax
|
|
|
|
|
jne unpend_V
|
|
|
|
|
popl %eax
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
#define BUILD_VEC(irq_num) \
|
|
|
|
|
ALIGN_TEXT ; \
|
|
|
|
|
vec/**/irq_num: ; \
|
|
|
|
|
int $ICU_OFFSET + (irq_num) ; \
|
|
|
|
|
popl %eax ; \
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
BUILD_VEC(0)
|
|
|
|
|
BUILD_VEC(1)
|
|
|
|
|
BUILD_VEC(2)
|
|
|
|
|
BUILD_VEC(3)
|
|
|
|
|
BUILD_VEC(4)
|
|
|
|
|
BUILD_VEC(5)
|
|
|
|
|
BUILD_VEC(6)
|
|
|
|
|
BUILD_VEC(7)
|
|
|
|
|
BUILD_VEC(8)
|
|
|
|
|
BUILD_VEC(9)
|
|
|
|
|
BUILD_VEC(10)
|
|
|
|
|
BUILD_VEC(11)
|
|
|
|
|
BUILD_VEC(12)
|
|
|
|
|
BUILD_VEC(13)
|
|
|
|
|
BUILD_VEC(14)
|
|
|
|
|
BUILD_VEC(15)
|
