2017-07-05 17:27:03 +00:00
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/******************************************************************************
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Copyright (c) 2001-2017, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixgbe.h"
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#ifdef IXGBE_FDIR
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void
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ixgbe_init_fdir(struct adapter *adapter)
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{
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u32 hdrm = 32 << fdir_pballoc;
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if (!(adapter->feat_en & IXGBE_FEATURE_FDIR))
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return;
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adapter->hw.mac.ops.setup_rxpba(&adapter->hw, 0, hdrm,
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PBA_STRATEGY_EQUAL);
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ixgbe_init_fdir_signature_82599(&adapter->hw, fdir_pballoc);
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} /* ixgbe_init_fdir */
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void
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2017-12-20 18:15:06 +00:00
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ixgbe_reinit_fdir(void *context)
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2017-07-05 17:27:03 +00:00
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{
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2017-12-20 18:15:06 +00:00
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if_ctx_t ctx = context;
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struct adapter *adapter = iflib_get_softc(ctx);
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struct ifnet *ifp = iflib_get_ifp(ctx);
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2017-07-05 17:27:03 +00:00
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if (!(adapter->feat_en & IXGBE_FEATURE_FDIR))
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return;
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if (adapter->fdir_reinit != 1) /* Shouldn't happen */
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return;
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ixgbe_reinit_fdir_tables_82599(&adapter->hw);
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adapter->fdir_reinit = 0;
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/* re-enable flow director interrupts */
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
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/* Restart the interface */
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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} /* ixgbe_reinit_fdir */
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/************************************************************************
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* ixgbe_atr
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*
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* Parse packet headers so that Flow Director can make
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* a hashed filter table entry allowing traffic flows
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* to be identified and kept on the same cpu. This
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* would be a performance hit, but we only do it at
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* IXGBE_FDIR_RATE of packets.
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************************************************************************/
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void
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ixgbe_atr(struct tx_ring *txr, struct mbuf *mp)
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{
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struct adapter *adapter = txr->adapter;
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struct ix_queue *que;
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struct ip *ip;
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struct tcphdr *th;
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struct udphdr *uh;
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struct ether_vlan_header *eh;
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union ixgbe_atr_hash_dword input = {.dword = 0};
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union ixgbe_atr_hash_dword common = {.dword = 0};
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int ehdrlen, ip_hlen;
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u16 etype;
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eh = mtod(mp, struct ether_vlan_header *);
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if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
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ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
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etype = eh->evl_proto;
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} else {
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ehdrlen = ETHER_HDR_LEN;
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etype = eh->evl_encap_proto;
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}
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/* Only handling IPv4 */
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if (etype != htons(ETHERTYPE_IP))
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return;
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ip = (struct ip *)(mp->m_data + ehdrlen);
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ip_hlen = ip->ip_hl << 2;
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/* check if we're UDP or TCP */
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switch (ip->ip_p) {
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case IPPROTO_TCP:
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th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
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/* src and dst are inverted */
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common.port.dst ^= th->th_sport;
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common.port.src ^= th->th_dport;
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input.formatted.flow_type ^= IXGBE_ATR_FLOW_TYPE_TCPV4;
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break;
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case IPPROTO_UDP:
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uh = (struct udphdr *)((caddr_t)ip + ip_hlen);
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/* src and dst are inverted */
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common.port.dst ^= uh->uh_sport;
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common.port.src ^= uh->uh_dport;
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input.formatted.flow_type ^= IXGBE_ATR_FLOW_TYPE_UDPV4;
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break;
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default:
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return;
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}
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input.formatted.vlan_id = htobe16(mp->m_pkthdr.ether_vtag);
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if (mp->m_pkthdr.ether_vtag)
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common.flex_bytes ^= htons(ETHERTYPE_VLAN);
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else
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common.flex_bytes ^= etype;
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common.ip ^= ip->ip_src.s_addr ^ ip->ip_dst.s_addr;
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que = &adapter->queues[txr->me];
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/*
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* This assumes the Rx queue and Tx
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* queue are bound to the same CPU
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*/
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ixgbe_fdir_add_signature_filter_82599(&adapter->hw,
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input, common, que->msix);
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} /* ixgbe_atr */
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#else
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/* TASK_INIT needs this function defined regardless if it's enabled */
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void
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2017-12-20 18:15:06 +00:00
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ixgbe_reinit_fdir(void *context)
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2017-07-05 17:27:03 +00:00
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{
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2017-12-20 18:15:06 +00:00
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UNREFERENCED_PARAMETER(context);
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2017-07-05 17:27:03 +00:00
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} /* ixgbe_reinit_fdir */
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void
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ixgbe_atr(struct tx_ring *txr, struct mbuf *mp)
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{
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UNREFERENCED_2PARAMETER(txr, mp);
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} /* ixgbe_atr */
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#endif
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