224 lines
5.9 KiB
ArmAsm
224 lines
5.9 KiB
ArmAsm
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/* $NetBSD: sa11x0_irq.S,v 1.5 2003/03/31 19:52:35 chris Exp $ */
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/*
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* Copyright (c) 1998 Mark Brinicombe.
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* Copyright (c) 1998 Causality Limited
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* All rights reserved.
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*
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* This code is derived from software contributed to the NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "assym.s"
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#include <machine/asm.h>
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#include <machine/armreg.h>
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#include <machine/asmacros.h>
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#include <arm/sa11x0/sa11x0_reg.h>
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__FBSDID("$FreeBSD$");
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Lcurrent_spl_level:
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.word _C_LABEL(current_spl_level)
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Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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Lspl_masks:
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.word _C_LABEL(spl_masks)
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.globl _C_LABEL(saipic_base)
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_C_LABEL(saipic_base):
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.word 0x00000000
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#ifdef INTR_DEBUG
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Ldbg_str:
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.asciz "irq_entry %x %x\n"
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#endif
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AST_ALIGNMENT_FAULT_LOCALS
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/*
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* Regsister usage
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*
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* r6 - Address of current handler
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* r7 - Pointer to handler pointer list
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of SAIP
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*/
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#define _SPL_LEVELS 13 /* XXX */
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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ENABLE_ALIGNMENT_FAULTS
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/* Load r8 with the SAIPIC interrupt requests */
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ldr r10, _C_LABEL(saipic_base)
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ldr r8, [r10, #(SAIPIC_IP)] /* Load IRQ pending register */
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#ifdef INTR_DEBUG
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ldr r2, [r10, #(SAIPIC_MR)]
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adr r0, Ldbg_str
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mov r1, r8
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bl _C_LABEL(printf)
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#endif
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/*
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* Note that we have entered the IRQ handler.
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* We are in SVC mode so we cannot use the processor mode
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* to determine if we are in an IRQ. Instead we will count the
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* each time the interrupt handler is nested.
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*/
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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/*
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* Need to block all interrupts at the IPL or lower for
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* all asserted interrupts.
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* This basically emulates hardware interrupt priority levels.
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* Means we need to go through the interrupt mask and for
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* every asserted interrupt we need to mask out all other
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* interrupts at the same or lower IPL.
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* If only we could wait until the main loop but we need to sort
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* this out first so interrupts can be re-enabled.
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*
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* This would benefit from a special ffs type routine
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*/
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mov r9, #(_SPL_LEVELS - 1)
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ldr r7, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r7, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r7, r9, lsl #2]
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mvn r2, r2
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ldr r0, Lcurrent_spl_level
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ldr r1, [r0]
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str r9, [r0]
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stmfd sp!, {r1}
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/* Update the SAIP irq masks */
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bl _C_LABEL(irq_setmasks)
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#ifdef INTR_DEBUG
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stmfd sp!, {r0,r1,r2}
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adr r0, Ldbg_str
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mov r2, r9
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bl _C_LABEL(printf)
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ldmia sp!, {r0,r1,r2}
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#endif
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mrs r0, cpsr_all /* Enable IRQ's */
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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mov r0, r8
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bl _C_LABEL(arm_handler_execute)
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ldmfd sp!, {r2}
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ldr r1, Lcurrent_spl_level
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str r2, [r1]
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/* Restore previous disabled mask */
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bl _C_LABEL(irq_setmasks)
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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#ifdef INTR_DEBUG
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adr r0, Ldbg_str
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mov r1, #3
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ldr r2, [r10, #(SAIPIC_MR)]
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bl _C_LABEL(printf)
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#endif
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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sub r1, r1, #1
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str r1, [r0]
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DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
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PULLFRAMEFROMSVCANDEXIT
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/* NOT REACHED */
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b . - 8
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ENTRY(irq_setmasks)
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/* Disable interrupts */
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit)
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msr cpsr_all, r1
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/* Calculate interrupt mask */
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ldr r0, Lspl_masks
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ldr r2, Lcurrent_spl_level
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ldr r2, [r2]
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ldr r2, [r0, r2, lsl #2]
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ldr r0, _C_LABEL(saipic_base)
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str r2, [r0, #(SAIPIC_MR)] /* Set mask register */
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/* Restore old cpsr and exit */
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/* msr cpsr_all, r3 XXX: not now.*/
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mov pc, lr
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Lcnt:
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.word _C_LABEL(cnt)
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#ifdef IRQSTATS
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Lintrcnt:
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.word _C_LABEL(intrcnt)
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#endif
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Lirqhandlers:
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.word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */
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.global _C_LABEL(intrnames), _C_LABEL(eintrnames)
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.global _C_LABEL(eintrcnt)
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_C_LABEL(intrnames):
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_C_LABEL(eintrnames):
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_C_LABEL(eintrcnt):
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.globl _C_LABEL(intrcnt), _C_LABEL(sintrcnt)
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_C_LABEL(intrcnt):
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.space ICU_LEN*4 /* XXX Should be linked to number of interrupts */
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_C_LABEL(sintrcnt):
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.space 32*4
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