2015-01-28 16:08:07 +00:00
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/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_HWPMC_ARMV7_H_
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#define _DEV_HWPMC_ARMV7_H_
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#define ARMV7_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
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PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
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PMC_CAP_THRESHOLD | PMC_CAP_READ | \
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PMC_CAP_WRITE | PMC_CAP_INVERT | \
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PMC_CAP_QUALIFIER)
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#define ARMV7_PMNC_ENABLE (1 << 0) /* Enable all counters */
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#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
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#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
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#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define ARMV7_PMNC_X (1 << 4) /* Export to ext. monitoring (ETM) */
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#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters implemented */
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#define ARMV7_PMNC_N_MASK 0x1f
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#define ARMV7_PMNC_MASK 0x3f /* Writable bits */
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2015-06-10 12:42:30 +00:00
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#define ARMV7_IDCODE_SHIFT 16 /* Identification code */
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#define ARMV7_IDCODE_MASK (0xff << ARMV7_IDCODE_SHIFT)
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#define ARMV7_IDCODE_CORTEX_A9 9
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#define ARMV7_IDCODE_CORTEX_A8 8
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2015-01-28 16:08:07 +00:00
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#define ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R))
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#define ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
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2015-06-10 12:42:30 +00:00
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#define EVENT_ID_MASK 0xFF
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2015-01-28 16:08:07 +00:00
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#ifdef _KERNEL
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/* MD extension for 'struct pmc' */
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struct pmc_md_armv7_pmc {
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uint32_t pm_armv7_evsel;
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};
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#endif /* _KERNEL */
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#endif /* _DEV_HWPMC_ARMV7_H_ */
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