82 lines
3.4 KiB
C
82 lines
3.4 KiB
C
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/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TI_EDMA3_H_
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#define _TI_EDMA3_H_
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/* Direct Mapped EDMA3 Events */
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#define TI_EDMA3_EVENT_SDTXEVT1 2
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#define TI_EDMA3_EVENT_SDRXEVT1 3
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#define TI_EDMA3_EVENT_SDTXEVT0 24
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#define TI_EDMA3_EVENT_SDRXEVT0 25
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struct ti_edma3cc_param_set {
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struct {
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uint32_t sam:1; /* Source address mode */
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uint32_t dam:1; /* Destination address mode */
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uint32_t syncdim:1; /* Transfer synchronization dimension */
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uint32_t static_set:1; /* Static Set */
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uint32_t :4;
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uint32_t fwid:3; /* FIFO Width */
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uint32_t tccmode:1; /* Transfer complete code mode */
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uint32_t tcc:6; /* Transfer complete code */
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uint32_t :2;
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uint32_t tcinten:1; /* Transfer complete interrupt enable */
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uint32_t itcinten:1; /* Intermediate xfer completion intr. ena */
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uint32_t tcchen:1; /* Transfer complete chaining enable */
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uint32_t itcchen:1; /* Intermediate xfer completion chaining ena */
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uint32_t privid:4; /* Privilege identification */
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uint32_t :3;
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uint32_t priv:1; /* Privilege level */
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} opt;
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uint32_t src; /* Channel Source Address */
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uint16_t acnt; /* Count for 1st Dimension */
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uint16_t bcnt; /* Count for 2nd Dimension */
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uint32_t dst; /* Channel Destination Address */
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int16_t srcbidx; /* Source B Index */
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int16_t dstbidx; /* Destination B Index */
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uint16_t link; /* Link Address */
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uint16_t bcntrld; /* BCNT Reload */
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int16_t srccidx; /* Source C Index */
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int16_t dstcidx; /* Destination C Index */
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uint16_t ccnt; /* Count for 3rd Dimension */
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uint16_t reserved; /* Reserved */
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};
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void ti_edma3_init(unsigned int eqn);
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int ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn);
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int ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn);
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int ti_edma3_enable_transfer_manual(unsigned int ch);
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int ti_edma3_enable_transfer_qdma(unsigned int ch);
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int ti_edma3_enable_transfer_event(unsigned int ch);
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void ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs);
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void ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs);
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#endif /* _TI_EDMA3_H_ */
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