64 lines
2.4 KiB
C
64 lines
2.4 KiB
C
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/*-
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* Copyright (c) 2015 Michael Gmelin <freebsd@grem.de>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ISL_H_
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#define _ISL_H_
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/* Command register 1 (bits 7-5) */
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#define REG_CMD1 0x00
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#define CMD1_MASK_POWER_DOWN 0x00 /* 00000000 */
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#define CMD1_MASK_ALS_ONCE 0x01 << 5 /* 00100000 */
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#define CMD1_MASK_IR_ONCE 0x02 << 5 /* 01000000 */
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#define CMD1_MASK_PROX_ONCE 0x03 << 5 /* 01100000 */
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/* RESERVED */ /* 10000000 */
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#define CMD1_MASK_ALS_CONT 0x05 << 5 /* 10100000 */
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#define CMD1_MASK_IR_CONT 0x06 << 5 /* 11000000 */
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#define CMD1_MASK_PROX_CONT 0x07 << 5 /* 11100000 */
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/* Command register 2 (bits) */
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#define REG_CMD2 0x01
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/* data registers */
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#define REG_DATA1 0x02
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#define REG_DATA2 0x03
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#define CMD2_SHIFT_RANGE 0x00
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#define CMD2_MASK_RANGE (0x03 << CMD2_SHIFT_RANGE)
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#define CMD2_SHIFT_RESOLUTION 0x02
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#define CMD2_MASK_RESOLUTION (0x03 << CMD2_SHIFT_RESOLUTION)
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/* Interrupt registers */
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#define REG_INT_LO_LSB 0x04
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#define REG_INT_LO_MSB 0x05
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#define REG_INT_HI_LSB 0x06
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#define REG_INT_HI_MSB 0x07
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/* Test register (should hold 0x00 at all times */
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#define REG_TEST 0x08
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#endif
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