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freebsd-skq/sys/mips/malta/gt_pci.c

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FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
/*-
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PCI configuration support for gt I/O Processor chip.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
#include <sys/endian.h>
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
#include <sys/interrupt.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cpu.h>
Fix path in all includes: remove /mips32 subdirectory
2008-09-10 03:49:08 +00:00
#include <mips/malta/maltareg.h>
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
Fix path in all includes: remove /mips32 subdirectory
2008-09-10 03:49:08 +00:00
#include <mips/malta/gtreg.h>
#include <mips/malta/gtvar.h>
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
#include <isa/isareg.h>
#include <dev/ic/i8259.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
Add PCI bus space implementation that converts all 2 and 4 bytes values to/from little endian according to PCI spec.
2013-08-30 20:28:35 +00:00
#include <mips/malta/gt_pci_bus_space.h>
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
#define ICU_LEN 16 /* number of ISA IRQs */
/*
* XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
* from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
*/
#define PIC_OCW1 1
#define PIC_OCW2 0
#define PIC_OCW3 0
#define OCW2_SELECT 0
#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
#define OCW3_POLL_PENDING (1U << 7)
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
/*
* Galileo controller's registers are LE so convert to then
* to/from native byte order. We rely on boot loader or emulator
* to set "swap bytes" configuration correctly for us
*/
#define GT_PCI_DATA(v) htole32((v))
#define GT_HOST_DATA(v) le32toh((v))
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
struct gt_pci_softc;
struct gt_pci_intr_cookie {
int irq;
struct gt_pci_softc *sc;
};
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
struct gt_pci_softc {
device_t sc_dev;
bus_space_tag_t sc_st;
bus_space_handle_t sc_ioh_icu1;
bus_space_handle_t sc_ioh_icu2;
bus_space_handle_t sc_ioh_elcr;
int sc_busno;
struct rman sc_mem_rman;
struct rman sc_io_rman;
struct rman sc_irq_rman;
Fix MALTA64 build.
2010-04-19 09:03:34 +00:00
unsigned long sc_mem;
bus_space_handle_t sc_io;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
struct resource *sc_irq;
struct intr_event *sc_eventstab[ICU_LEN];
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
uint16_t sc_imask;
uint16_t sc_elcr;
uint16_t sc_reserved;
void *sc_ih;
};
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
static void gt_pci_set_icus(struct gt_pci_softc *);
static int gt_pci_intr(void *v);
static int gt_pci_probe(device_t);
static int gt_pci_attach(device_t);
static int gt_pci_activate_resource(device_t, device_t, int, int,
struct resource *);
static int gt_pci_setup_intr(device_t, device_t, struct resource *,
int, driver_filter_t *, driver_intr_t *, void *, void **);
static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
static int gt_pci_maxslots(device_t );
static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
uint32_t *);
static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
uint32_t, int);
static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
int *, rman_res_t, rman_res_t, rman_res_t, u_int);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
static void
gt_pci_mask_irq(void *source)
{
struct gt_pci_intr_cookie *cookie = source;
struct gt_pci_softc *sc = cookie->sc;
int irq = cookie->irq;
sc->sc_imask |= (1 << irq);
sc->sc_elcr |= (1 << irq);
gt_pci_set_icus(sc);
}
static void
gt_pci_unmask_irq(void *source)
{
struct gt_pci_intr_cookie *cookie = source;
struct gt_pci_softc *sc = cookie->sc;
int irq = cookie->irq;
/* Enable it, set trigger mode. */
sc->sc_imask &= ~(1 << irq);
sc->sc_elcr &= ~(1 << irq);
gt_pci_set_icus(sc);
}
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
static void
gt_pci_set_icus(struct gt_pci_softc *sc)
{
/* Enable the cascade IRQ (2) if 8-15 is enabled. */
if ((sc->sc_imask & 0xff00) != 0xff00)
sc->sc_imask &= ~(1U << 2);
else
sc->sc_imask |= (1U << 2);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_imask & 0xff);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
(sc->sc_imask >> 8) & 0xff);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_elcr & 0xff);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
(sc->sc_elcr >> 8) & 0xff);
}
static int
gt_pci_intr(void *v)
{
struct gt_pci_softc *sc = v;
struct intr_event *event;
MFp4: Merge interrupt code from p4 Submitted by: gonzo@
2008-09-19 04:16:13 +00:00
int irq;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
for (;;) {
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW3_SEL | OCW3_P);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
if ((irq & OCW3_POLL_PENDING) == 0)
{
return FILTER_HANDLED;
}
irq = OCW3_POLL_IRQ(irq);
if (irq == 2) {
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
PIC_OCW3, OCW3_SEL | OCW3_P);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
PIC_OCW3);
if (irq & OCW3_POLL_PENDING)
irq = OCW3_POLL_IRQ(irq) + 8;
else
irq = 2;
}
event = sc->sc_eventstab[irq];
MFp4: Merge interrupt code from p4 Submitted by: gonzo@
2008-09-19 04:16:13 +00:00
if (!event || TAILQ_EMPTY(&event->ie_handlers))
continue;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
MFp4: Merge interrupt code from p4 Submitted by: gonzo@
2008-09-19 04:16:13 +00:00
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
/* XXX: Log stray IRQs */
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
/* Send a specific EOI to the 8259. */
if (irq > 7) {
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
OCW2_ILS(irq & 7));
irq = 2;
}
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
}
return FILTER_HANDLED;
}
static int
gt_pci_probe(device_t dev)
{
device_set_desc(dev, "GT64120 PCI bridge");
return (0);
}
static int
gt_pci_attach(device_t dev)
{
uint32_t busno;
struct gt_pci_softc *sc = device_get_softc(dev);
int rid;
busno = 0;
sc->sc_dev = dev;
sc->sc_busno = busno;
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
sc->sc_st = mips_bus_space_generic;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
/* Use KSEG1 to access IO ports for it is uncached */
Fixed FreeBSD/mips MALTA support for QEMU Recource management functions in GT PCI controller driver treated memory/IO resources as KSEG1 addresses, later during activation these values would be increased by KSEG1 base again rendering the address invalid and causing "bus error" trap. Actual logic was converted to use real physical addresses, so mapping takes place only during activation. Submitted by: Aleksandr Rybalko <ray@FreeBSD.org> Approved by: re (gjb)
2016-06-29 23:33:44 +00:00
sc->sc_io = MALTA_PCI0_IO_BASE;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
Fixes for compatibility with QEMU: - Route PCI interrupt for NIC - Make "no mapping" warning more user-friendly: add device name and mention that it's IRQ mapping - Do not overlap ICUs' IO window with PCI devices' IO windows by starting IO rman at offset 0x100
2013-08-27 01:40:13 +00:00
/*
* First 256 bytes are ISA's registers: e.g. i8259's
* So do not use them for general purpose PCI I/O window
*/
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
if (rman_init(&sc->sc_io_rman) != 0 ||
Fixes for compatibility with QEMU: - Route PCI interrupt for NIC - Make "no mapping" warning more user-friendly: add device name and mention that it's IRQ mapping - Do not overlap ICUs' IO window with PCI devices' IO windows by starting IO rman at offset 0x100
2013-08-27 01:40:13 +00:00
rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
panic("gt_pci_attach: failed to set up I/O rman");
}
/* Use KSEG1 to access PCI memory for it is uncached */
Fixed FreeBSD/mips MALTA support for QEMU Recource management functions in GT PCI controller driver treated memory/IO resources as KSEG1 addresses, later during activation these values would be increased by KSEG1 base again rendering the address invalid and causing "bus error" trap. Actual logic was converted to use real physical addresses, so mapping takes place only during activation. Submitted by: Aleksandr Rybalko <ray@FreeBSD.org> Approved by: re (gjb)
2016-06-29 23:33:44 +00:00
sc->sc_mem = MALTA_PCIMEM1_BASE;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman,
sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
panic("gt_pci_attach: failed to set up memory rman");
}
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
panic("gt_pci_attach: failed to set up IRQ rman");
/*
* Map the PIC/ELCR registers.
*/
#if 0
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
device_printf(dev, "unable to map ELCR registers\n");
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
device_printf(dev, "unable to map ICU1 registers\n");
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
device_printf(dev, "unable to map ICU2 registers\n");
#else
Fixed FreeBSD/mips MALTA support for QEMU Recource management functions in GT PCI controller driver treated memory/IO resources as KSEG1 addresses, later during activation these values would be increased by KSEG1 base again rendering the address invalid and causing "bus error" trap. Actual logic was converted to use real physical addresses, so mapping takes place only during activation. Submitted by: Aleksandr Rybalko <ray@FreeBSD.org> Approved by: re (gjb)
2016-06-29 23:33:44 +00:00
sc->sc_ioh_elcr = MIPS_PHYS_TO_KSEG1(sc->sc_io + 0x4d0);
sc->sc_ioh_icu1 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU1);
sc->sc_ioh_icu2 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU2);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
#endif
/* All interrupts default to "masked off". */
sc->sc_imask = 0xffff;
/* All interrupts default to edge-triggered. */
sc->sc_elcr = 0;
/*
* Initialize the 8259s.
*/
/* reset, program device, 4 bytes */
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
ICW1_RESET | ICW1_IC4);
/*
* XXX: values from NetBSD's <dev/ic/i8259reg.h>
*/
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
0/*XXX*/);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
1 << 2);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
ICW4_8086);
/* mask all interrupts */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_imask & 0xff);
/* enable special mask mode */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW3_SEL | OCW3_ESMM | OCW3_SMM);
/* read IRR by default */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW3_SEL | OCW3_RR);
/* reset, program device, 4 bytes */
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
ICW1_RESET | ICW1_IC4);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
0/*XXX*/);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
1 << 2);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
ICW4_8086);
/* mask all interrupts */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_imask & 0xff);
/* enable special mask mode */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW3_SEL | OCW3_ESMM | OCW3_SMM);
/* read IRR by default */
The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>
2011-07-16 00:30:23 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
OCW3_SEL | OCW3_RR);
/*
* Default all interrupts to edge-triggered.
*/
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
sc->sc_elcr & 0xff);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
(sc->sc_elcr >> 8) & 0xff);
/*
* Some ISA interrupts are reserved for devices that
* we know are hard-wired to certain IRQs.
*/
sc->sc_reserved =
(1U << 0) | /* timer */
(1U << 1) | /* keyboard controller (keyboard) */
(1U << 2) | /* PIC cascade */
(1U << 3) | /* COM 2 */
(1U << 4) | /* COM 1 */
(1U << 6) | /* floppy */
(1U << 7) | /* centronics */
(1U << 8) | /* RTC */
(1U << 9) | /* I2C */
(1U << 12) | /* keyboard controller (mouse) */
(1U << 14) | /* IDE primary */
(1U << 15); /* IDE secondary */
/* Hook up our interrupt handler. */
if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return ENXIO;
}
if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
gt_pci_intr, NULL, sc, &sc->sc_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return ENXIO;
}
/* Initialize memory and i/o rmans. */
Add domain support to PCI bus allocation When the system has more than a single PCI domain, the bus numbers are not unique, thus they cannot be used for "pci" device numbering. Change bus numbers to -1 (i.e. to-be-determined automatically) wherever the code did not care about domains. Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3406
2015-09-16 23:34:51 +00:00
device_add_child(dev, "pci", -1);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
return (bus_generic_attach(dev));
}
static int
gt_pci_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static int
gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
int reg, uint32_t *addr)
{
*addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
return (0);
}
static uint32_t
Fix MALTA build; some prototypes were wrong and blew up when kobj method signature checking was turned on.
2009-06-12 22:49:35 +00:00
gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
int bytes)
{
struct gt_pci_softc *sc = device_get_softc(dev);
uint32_t data;
uint32_t addr;
uint32_t shift, mask;
if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
return (uint32_t)(-1);
/* Clear cause register bits. */
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Discussed with: -arch, rdivacky Reviewed by: cperciva
2013-11-30 22:17:27 +00:00
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
/*
* Galileo system controller is special
*/
if ((bus == 0) && (slot == 0))
data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
else
data = GT_REGVAL(GT_PCI0_CFG_DATA);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
/* Check for master abort. */
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
data = (uint32_t) -1;
switch(reg % 4)
{
case 3:
shift = 24;
break;
case 2:
shift = 16;
break;
case 1:
shift = 8;
break;
default:
shift = 0;
break;
}
switch(bytes)
{
case 1:
mask = 0xff;
data = (data >> shift) & mask;
break;
case 2:
mask = 0xffff;
if(reg % 4 == 0)
data = data & mask;
else
data = (data >> 16) & mask;
break;
case 4:
break;
default:
panic("gt_pci_readconfig: wrong bytes count");
break;
}
#if 0
printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
bus, slot, func, reg, data, bytes);
#endif
return (data);
}
static void
Fix MALTA build; some prototypes were wrong and blew up when kobj method signature checking was turned on.
2009-06-12 22:49:35 +00:00
gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
uint32_t data, int bytes)
{
struct gt_pci_softc *sc = device_get_softc(dev);
uint32_t addr;
uint32_t reg_data;
uint32_t shift, mask;
if(bytes != 4)
{
reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
o Simplify code: trade 15 lines of case for one multiplication
2009-01-14 22:32:43 +00:00
shift = 8 * (reg & 3);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
switch(bytes)
{
case 1:
mask = 0xff;
data = (reg_data & ~ (mask << shift)) | (data << shift);
break;
case 2:
mask = 0xffff;
if(reg % 4 == 0)
data = (reg_data & ~mask) | data;
else
data = (reg_data & ~ (mask << shift)) |
(data << shift);
break;
case 4:
break;
default:
panic("gt_pci_readconfig: wrong bytes count");
break;
}
}
if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
return;
/* The galileo has problems accessing device 31. */
if (bus == 0 && slot == 31)
return;
/* XXX: no support for bus > 0 yet */
if (bus > 0)
return;
/* Clear cause register bits. */
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Discussed with: -arch, rdivacky Reviewed by: cperciva
2013-11-30 22:17:27 +00:00
GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
Fix GT PCI controller driver on big-endian hardware
2013-08-28 01:10:51 +00:00
/*
* Galileo system controller is special
*/
if ((bus == 0) && (slot == 0))
GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
else
GT_REGVAL(GT_PCI0_CFG_DATA) = data;
#if 0
printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
bus, slot, func, reg, data, bytes);
#endif
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
}
static int
gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
/* struct gt_pci_softc *sc = device_get_softc(pcib); */
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
/*
* XXXMIPS: We need routing logic. This is just a stub .
*/
switch (device) {
case 9: /*
* PIIX4 IDE adapter. HW IRQ0
*/
return 0;
Fixes for compatibility with QEMU: - Route PCI interrupt for NIC - Make "no mapping" warning more user-friendly: add device name and mention that it's IRQ mapping - Do not overlap ICUs' IO window with PCI devices' IO windows by starting IO rman at offset 0x100
2013-08-27 01:40:13 +00:00
case 11: /* Ethernet */
return 10;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
default:
Fixes for compatibility with QEMU: - Route PCI interrupt for NIC - Make "no mapping" warning more user-friendly: add device name and mention that it's IRQ mapping - Do not overlap ICUs' IO window with PCI devices' IO windows by starting IO rman at offset 0x100
2013-08-27 01:40:13 +00:00
device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
}
return (0);
}
static int
gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct gt_pci_softc *sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = sc->sc_busno;
return (0);
}
return (ENOENT);
}
static int
gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
struct gt_pci_softc * sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_BUS:
sc->sc_busno = result;
return (0);
}
return (ENOENT);
}
static struct resource *
gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
Convert rman to use rman_res_t instead of u_long Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
{
struct gt_pci_softc *sc = device_get_softc(bus);
struct resource *rv = NULL;
struct rman *rm;
bus_space_handle_t bh = 0;
switch (type) {
case SYS_RES_IRQ:
rm = &sc->sc_irq_rman;
break;
case SYS_RES_MEMORY:
rm = &sc->sc_mem_rman;
bh = sc->sc_mem;
break;
case SYS_RES_IOPORT:
rm = &sc->sc_io_rman;
bh = sc->sc_io;
break;
default:
return (NULL);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
rman_set_rid(rv, *rid);
if (type != SYS_RES_IRQ) {
bh += (rman_get_start(rv));
Add PCI bus space implementation that converts all 2 and 4 bytes values to/from little endian according to PCI spec.
2013-08-30 20:28:35 +00:00
rman_set_bustag(rv, gt_pci_bus_space);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
rman_set_bushandle(rv, bh);
if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
}
return (rv);
}
static int
gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
bus_space_handle_t p;
int error;
if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
error = bus_space_map(rman_get_bustag(r),
rman_get_bushandle(r), rman_get_size(r), 0, &p);
if (error)
return (error);
rman_set_bushandle(r, p);
}
return (rman_activate_resource(r));
}
static int
gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *handler,
void *arg, void **cookiep)
{
struct gt_pci_softc *sc = device_get_softc(dev);
struct intr_event *event;
int irq, error;
irq = rman_get_start(ires);
if (irq >= ICU_LEN || irq == 2)
panic("%s: bad irq or type", __func__);
event = sc->sc_eventstab[irq];
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
sc->sc_intr_cookies[irq].irq = irq;
sc->sc_intr_cookies[irq].sc = sc;
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
if (event == NULL) {
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
error = intr_event_create(&event,
(void *)&sc->sc_intr_cookies[irq], 0, irq,
gt_pci_mask_irq, gt_pci_unmask_irq,
NULL, NULL, "gt_pci intr%d:", irq);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
if (error)
return 0;
sc->sc_eventstab[irq] = event;
}
intr_event_add_handler(event, device_get_nameunit(child), filt,
handler, arg, intr_priority(flags), flags, cookiep);
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
return 0;
}
static int
gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
void *cookie)
{
Merge from projects/mips to head by hand: r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the BSP. Provide a missing prototype. r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. r196836 | gonzo | 2009-09-04 13:02:11 -0600 (Fri, 04 Sep 2009) | 2 lines - Clean out some XXXMIPS comments that's not relevant now r196236 | imp | 2009-08-14 19:03:13 -0600 (Fri, 14 Aug 2009) | 3 lines Fix style error replicated multiple times. Move to mips_bus_space_generic for octeon obio impl. r195496 | imp | 2009-07-09 09:04:52 -0600 (Thu, 09 Jul 2009) | 2 lines Don't force ISA_MIPS32. r195495 | imp | 2009-07-09 09:04:24 -0600 (Thu, 09 Jul 2009) | 4 lines Make the yamon function pointer stuff 64-bit safe. Make the base unsigned long, and sign extend the address of the function we're calling through. r195494 | imp | 2009-07-09 08:54:09 -0600 (Thu, 09 Jul 2009) | 3 lines Addresses should be unsigned long. Make the address constants unsigned long. r194929 | gonzo | 2009-06-24 16:42:52 -0600 (Wed, 24 Jun 2009) | 6 lines - Do not use hardcoded uart speed - Call mips_timer_early_init before initializing uart in order to make DELAY usable for ns8250 driver Submitted by: Neelkanth Natu r194212 | gonzo | 2009-06-14 14:54:46 -0600 (Sun, 14 Jun 2009) | 2 lines - Fix prototypes to make compiler happy r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines - Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default we assume that there is no FPU, because majority of SoC does not have it. r192788 | gonzo | 2009-05-25 22:51:56 -0600 (Mon, 25 May 2009) | 3 lines - Provide proper pre_thread/post_ithread functions for GT PCI controller. r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines - Make mips_bus_space_generic be of type bus_space_tag_t instead of struct bus_space and update all relevant places. r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines Use FreeBSD/arm approach for handling bus space access: space tag is a pointer to bus_space structure that defines access methods and hence every bus can define own accessors. Default space is mips_bus_space_generic. It's a simple interface to physical memory, values are read with regard to host system byte order.
2010-01-10 20:06:14 +00:00
struct gt_pci_softc *sc = device_get_softc(dev);
int irq;
irq = rman_get_start(res);
gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
return (intr_event_remove_handler(cookie));
}
static device_method_t gt_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, gt_pci_probe),
DEVMETHOD(device_attach, gt_pci_attach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_read_ivar, gt_read_ivar),
DEVMETHOD(bus_write_ivar, gt_write_ivar),
DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
DEVMETHOD(pcib_read_config, gt_pci_read_config),
DEVMETHOD(pcib_write_config, gt_pci_write_config),
DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
Convert PCIe Hot Plug to using pci_request_feature Convert PCIe hot plug support over to asking the firmware, if any, for permission to use the HotPlug hardware. Implement pci_request_feature for ACPI. All other host pci connections to allowing all valid feature requests. Sponsored by: Netflix
2017-02-25 06:11:59 +00:00
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
- There's no need to overwrite the default device method with the default one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
DEVMETHOD_END
FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64, mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
};
static driver_t gt_pci_driver = {
"pcib",
gt_pci_methods,
sizeof(struct gt_pci_softc),
};
static devclass_t gt_pci_devclass;
DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
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