2010-04-14 20:45:33 +00:00
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/*-
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* Copyright (c) 2008, 2009, 2010 Nikolay Denev <ndenev@gmail.com>
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* Copyright (c) 2007, 2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
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* THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_SGEREG_H
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#define _IF_SGEREG_H
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/*
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* SiS PCI vendor ID.
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*/
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#define SIS_VENDORID 0x1039
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/*
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* SiS PCI device IDs
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*/
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#define SIS_DEVICEID_190 0x0190
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#define SIS_DEVICEID_191 0x0191
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#define TX_CTL 0x00
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#define TX_DESC 0x04
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#define Reserved0 0x08
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#define TX_NEXT 0x0c
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#define RX_CTL 0x10
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#define RX_DESC 0x14
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#define Reserved1 0x18
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#define RX_NEXT 0x1c
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#define IntrStatus 0x20
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#define IntrMask 0x24
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#define IntrControl 0x28
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#define IntrTimer 0x2c
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#define PMControl 0x30
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#define Reserved2 0x34
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#define ROMControl 0x38
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#define ROMInterface 0x3c
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#define StationControl 0x40
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#define GMIIControl 0x44
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#define GMacIOCR 0x48
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#define GMacIOCTL 0x4c
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#define TxMacControl 0x50
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#define TxMacTimeLimit 0x54
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#define RGMIIDelay 0x58
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#define Reserved3 0x5c
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#define RxMacControl 0x60 /* 1 WORD */
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#define RxMacAddr 0x62 /* 6x BYTE */
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#define RxHashTable 0x68 /* 1 LONG */
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#define RxHashTable2 0x6c /* 1 LONG */
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#define RxWakeOnLan 0x70
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#define RxWakeOnLanData 0x74
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#define RxMPSControl 0x78
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#define Reserved4 0x7c
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/*
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* IntrStatus Register Content
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*/
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#define INTR_SOFT 0x40000000
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#define INTR_TIMER 0x20000000
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#define INTR_PAUSE_FRAME 0x00080000
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#define INTR_MAGIC_FRAME 0x00040000
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#define INTR_WAKE_FRAME 0x00020000
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#define INTR_LINK 0x00010000
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#define INTR_RX_IDLE 0x00000080
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#define INTR_RX_DONE 0x00000040
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#define INTR_TXQ1_IDLE 0x00000020
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#define INTR_TXQ1_DONE 0x00000010
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#define INTR_TX_IDLE 0x00000008
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#define INTR_TX_DONE 0x00000004
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#define INTR_RX_HALT 0x00000002
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#define INTR_TX_HALT 0x00000001
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#define SGE_INTRS \
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(INTR_RX_IDLE | INTR_RX_DONE | INTR_TXQ1_IDLE | \
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INTR_TXQ1_DONE |INTR_TX_IDLE | INTR_TX_DONE | \
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INTR_TX_HALT | INTR_RX_HALT)
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/*
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* RxStatusDesc Register Content
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*/
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#define RxRES 0x00200000
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#define RxCRC 0x00080000
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#define RxRUNT 0x00100000
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#define RxRWT 0x00400000
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/*
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* RX_CTL Register Content
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*/
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#define RX_CTL_POLL 0x00000010
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#define RX_CTL_ENB 0x00000001
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/*
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* TX_CTL Register Content
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*/
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#define TX_CTL_POLL 0x00000010
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#define TX_CTL_ENB 0x00000001
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/*
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* RxMacControl Register Content
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*/
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#define AcceptBroadcast 0x0800
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#define AcceptMulticast 0x0400
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#define AcceptMyPhys 0x0200
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#define AcceptAllPhys 0x0100
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#define AcceptErr 0x0020
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#define AcceptRunt 0x0010
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2010-04-29 18:00:42 +00:00
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#define RXMAC_STRIP_FCS 0x0010
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#define RXMAC_PAD_ENB 0x0004
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#define SGE_RX_PAD_BYTES 10
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2010-04-14 20:45:33 +00:00
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/* Station control register. */
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#define SC_LOOPBACK 0x80000000
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#define SC_RGMII 0x00008000
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#define SC_FDX 0x00001000
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#define SC_SPEED_MASK 0x00000c00
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#define SC_SPEED_10 0x00000400
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#define SC_SPEED_100 0x00000800
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#define SC_SPEED_1000 0x00000c00
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/*
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* Gigabit Media Independent Interface CTL register
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*/
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#define GMI_DATA 0xffff0000
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#define GMI_DATA_SHIFT 16
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#define GMI_REG 0x0000f800
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#define GMI_REG_SHIFT 11
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#define GMI_PHY 0x000007c0
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#define GMI_PHY_SHIFT 6
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#define GMI_OP_WR 0x00000020
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#define GMI_OP_RD 0x00000000
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#define GMI_REQ 0x00000010
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#define GMI_MDIO 0x00000008
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#define GMI_MDDIR 0x00000004
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#define GMI_MDC 0x00000002
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#define GMI_MDEN 0x00000001
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/* Tx descriptor command bits. */
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#define TDC_OWN 0x80000000
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#define TDC_INTR 0x40000000
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#define TDC_THOL3 0x30000000
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#define TDC_THOL2 0x20000000
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#define TDC_THOL1 0x10000000
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#define TDC_THOL0 0x00000000
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#define TDC_LS 0x08000000
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#define TDC_IP_CSUM 0x04000000
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#define TDC_TCP_CSUM 0x02000000
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#define TDC_UDP_CSUM 0x01000000
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#define TDC_BST 0x00800000
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#define TDC_EXT 0x00400000
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#define TDC_DEF 0x00200000
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#define TDC_BKF 0x00100000
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#define TDC_CRS 0x00080000
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#define TDC_COL 0x00040000
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#define TDC_CRC 0x00020000
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#define TDC_PAD 0x00010000
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#define SGE_TX_INTR_FRAMES 32
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/*
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* TX descriptor status bits.
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*/
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#define TDS_OWC 0x00080000
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#define TDS_ABT 0x00040000
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#define TDS_FIFO 0x00020000
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#define TDS_CRS 0x00010000
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#define TDS_COLLS 0x0000ffff
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#define SGE_TX_ERROR(x) ((x) & (TDS_OWC | TDS_ABT | TDS_FIFO | TDS_CRS))
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#define TX_ERR_BITS "\20" \
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"\21CRS\22FIFO\23ABT\24OWC"
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/* Rx descriptor command bits. */
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#define RDC_OWN 0x80000000
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#define RDC_INTR 0x40000000
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#define RDC_IP_CSUM 0x20000000
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#define RDC_TCP_CSUM 0x10000000
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#define RDC_UDP_CSUM 0x08000000
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#define RDC_IP_CSUM_OK 0x04000000
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#define RDC_TCP_CSUM_OK 0x02000000
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#define RDC_UDP_CSUM_OK 0x01000000
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#define RDC_WAKEUP 0x00400000
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#define RDC_MAGIC 0x00200000
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#define RDC_PAUSE 0x00100000
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#define RDC_BCAST 0x000c0000
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#define RDC_MCAST 0x00080000
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#define RDC_UCAST 0x00040000
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#define RDC_CRCOFF 0x00020000
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#define RDC_PREADD 0x00010000
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/*
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* RX descriptor status bits
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*/
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#define RDS_TAGON 0x80000000
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#define RDS_DESCS 0x3f000000
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#define RDS_ABORT 0x00800000
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#define RDS_SHORT 0x00400000
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#define RDS_LIMIT 0x00200000
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#define RDS_MIIER 0x00100000
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#define RDS_OVRUN 0x00080000
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#define RDS_NIBON 0x00040000
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#define RDS_COLON 0x00020000
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#define RDS_CRCOK 0x00010000
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#define SGE_RX_ERROR(x) \
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((x) & (RDS_COLON | RDS_NIBON | RDS_OVRUN | RDS_MIIER | \
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RDS_LIMIT | RDS_SHORT | RDS_ABORT))
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#define SGE_RX_NSEGS(x) (((x) & RDS_DESCS) >> 24)
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#define RX_ERR_BITS "\20" \
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"\21CRCOK\22COLON\23NIBON\24OVRUN" \
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"\25MIIER\26LIMIT\27SHORT\30ABORT" \
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"\40TAGON"
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#define RING_END 0x80000000
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#define SGE_RX_BYTES(x) ((x) & 0xFFFF)
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#define SGE_INC(x, y) (x) = (((x) + 1) % y)
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/* Taken from Solaris driver */
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#define EI_DATA 0xffff0000
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#define EI_DATA_SHIFT 16
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#define EI_OFFSET 0x0000fc00
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#define EI_OFFSET_SHIFT 10
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#define EI_OP 0x00000300
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#define EI_OP_SHIFT 8
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#define EI_OP_RD (2 << EI_OP_SHIFT)
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#define EI_OP_WR (1 << EI_OP_SHIFT)
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#define EI_REQ 0x00000080
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#define EI_DO 0x00000008
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#define EI_DI 0x00000004
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#define EI_CLK 0x00000002
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#define EI_CS 0x00000001
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/*
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* EEPROM Addresses
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*/
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#define EEPROMSignature 0x00
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#define EEPROMCLK 0x01
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#define EEPROMInfo 0x02
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#define EEPROMMACAddr 0x03
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struct sge_desc {
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uint32_t sge_sts_size;
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uint32_t sge_cmdsts;
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uint32_t sge_ptr;
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uint32_t sge_flags;
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};
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#define SGE_RX_RING_CNT 256 /* [8, 1024] */
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#define SGE_TX_RING_CNT 256 /* [8, 8192] */
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#define SGE_DESC_ALIGN 16
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#define SGE_MAXTXSEGS 1
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#define SGE_RX_BUF_ALIGN sizeof(uint64_t)
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#define SGE_RX_RING_SZ (SGE_RX_RING_CNT * sizeof(struct sge_desc))
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#define SGE_TX_RING_SZ (SGE_TX_RING_CNT * sizeof(struct sge_desc))
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#define SGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
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struct sge_list_data {
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struct sge_desc *sge_rx_ring;
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struct sge_desc *sge_tx_ring;
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/* physical bus addresses of sge_rx_ring/sge_tx_ring */
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bus_addr_t sge_rx_paddr;
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bus_addr_t sge_tx_paddr;
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};
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struct sge_chain_data {
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bus_dma_tag_t sge_tag;
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bus_dma_tag_t sge_rx_tag;
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bus_dma_tag_t sge_tx_tag;
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bus_dmamap_t sge_rx_dmamap;
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bus_dmamap_t sge_tx_dmamap;
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bus_dma_tag_t sge_txmbuf_tag;
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bus_dma_tag_t sge_rxmbuf_tag;
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struct mbuf *sge_rx_mbuf[SGE_RX_RING_CNT];
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struct mbuf *sge_tx_mbuf[SGE_TX_RING_CNT];
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bus_dmamap_t sge_rx_map[SGE_RX_RING_CNT];
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bus_dmamap_t sge_rx_spare_map;
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bus_dmamap_t sge_tx_map[SGE_TX_RING_CNT];
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int sge_rx_cons;
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int sge_tx_prod;
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int sge_tx_cons;
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int sge_tx_cnt;
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};
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struct sge_type {
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uint16_t sge_vid;
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uint16_t sge_did;
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char *sge_name;
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};
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struct sge_softc {
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struct ifnet *sge_ifp; /* interface info */
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struct resource *sge_res;
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int sge_res_id;
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int sge_res_type;
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struct resource *sge_irq;
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void *sge_intrhand;
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device_t sge_dev;
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device_t sge_miibus;
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uint8_t sge_rev;
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struct sge_list_data sge_ldata;
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struct sge_chain_data sge_cdata;
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struct callout sge_stat_ch;
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int sge_timer;
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int sge_flags;
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#define SGE_FLAG_FASTETHER 0x0001
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2010-04-29 17:34:01 +00:00
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#define SGE_FLAG_SIS190 0x0002
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2010-04-14 20:45:33 +00:00
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#define SGE_FLAG_RGMII 0x0010
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#define SGE_FLAG_SPEED_1000 0x2000
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#define SGE_FLAG_FDX 0x4000
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#define SGE_FLAG_LINK 0x8000
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int sge_if_flags;
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int sge_intrcontrol;
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int sge_intrtimer;
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struct mtx sge_mtx;
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};
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#define SGE_LOCK(_sc) mtx_lock(&(_sc)->sge_mtx)
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#define SGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sge_mtx)
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#define SGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sge_mtx, MA_OWNED)
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#define SGE_TIMEOUT 1000
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#endif /* _IF_SGEREG_H */
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