2016-01-26 15:22:04 +00:00
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/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_udma_api API
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* @ingroup group_udma
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* UDMA API
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* @{
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* @}
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*
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* @defgroup group_udma_main UDMA Main
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* @ingroup group_udma_api
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* UDMA main API
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* @{
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* @file al_hal_udma.h
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*
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* @brief C Header file for the Universal DMA HAL driver
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*
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*/
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#ifndef __AL_HAL_UDMA_H__
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#define __AL_HAL_UDMA_H__
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#include "al_hal_common.h"
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#include "al_hal_udma_regs.h"
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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#define DMA_MAX_Q 4
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#define AL_UDMA_MIN_Q_SIZE 4
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#define AL_UDMA_MAX_Q_SIZE (1 << 16) /* hw can do more, but we limit it */
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/* Default Max number of descriptors supported per action */
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#define AL_UDMA_DEFAULT_MAX_ACTN_DESCS 16
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#define AL_UDMA_REV_ID_1 1
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#define AL_UDMA_REV_ID_2 2
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#define DMA_RING_ID_MASK 0x3
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/* New registers ?? */
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/* Statistics - TBD */
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/** UDMA submission descriptor */
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union al_udma_desc {
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/* TX */
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struct {
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uint32_t len_ctrl;
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uint32_t meta_ctrl;
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uint64_t buf_ptr;
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} tx;
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/* TX Meta, used by upper layer */
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struct {
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uint32_t len_ctrl;
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uint32_t meta_ctrl;
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uint32_t meta1;
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uint32_t meta2;
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} tx_meta;
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/* RX */
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struct {
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uint32_t len_ctrl;
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uint32_t buf2_ptr_lo;
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uint64_t buf1_ptr;
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} rx;
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} __packed_a16;
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/* TX desc length and control fields */
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#define AL_M2S_DESC_CONCAT AL_BIT(31) /* concatenate */
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#define AL_M2S_DESC_DMB AL_BIT(30)
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/** Data Memory Barrier */
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#define AL_M2S_DESC_NO_SNOOP_H AL_BIT(29)
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#define AL_M2S_DESC_INT_EN AL_BIT(28) /** enable interrupt */
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#define AL_M2S_DESC_LAST AL_BIT(27)
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#define AL_M2S_DESC_FIRST AL_BIT(26)
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#define AL_M2S_DESC_RING_ID_SHIFT 24
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#define AL_M2S_DESC_RING_ID_MASK (0x3 << AL_M2S_DESC_RING_ID_SHIFT)
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#define AL_M2S_DESC_META_DATA AL_BIT(23)
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#define AL_M2S_DESC_DUMMY AL_BIT(22) /* for Metdata only */
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#define AL_M2S_DESC_LEN_ADJ_SHIFT 20
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#define AL_M2S_DESC_LEN_ADJ_MASK (0x7 << AL_M2S_DESC_LEN_ADJ_SHIFT)
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#define AL_M2S_DESC_LEN_SHIFT 0
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#define AL_M2S_DESC_LEN_MASK (0xfffff << AL_M2S_DESC_LEN_SHIFT)
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#define AL_S2M_DESC_DUAL_BUF AL_BIT(31)
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#define AL_S2M_DESC_NO_SNOOP_H AL_BIT(29)
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#define AL_S2M_DESC_INT_EN AL_BIT(28) /** enable interrupt */
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#define AL_S2M_DESC_RING_ID_SHIFT 24
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#define AL_S2M_DESC_RING_ID_MASK (0x3 << AL_S2M_DESC_RING_ID_SHIFT)
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#define AL_S2M_DESC_LEN_SHIFT 0
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#define AL_S2M_DESC_LEN_MASK (0xffff << AL_S2M_DESC_LEN_SHIFT)
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#define AL_S2M_DESC_LEN2_SHIFT 16
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#define AL_S2M_DESC_LEN2_MASK (0x3fff << AL_S2M_DESC_LEN2_SHIFT)
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#define AL_S2M_DESC_LEN2_GRANULARITY_SHIFT 6
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2016-09-06 14:59:13 +00:00
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/* TX/RX descriptor Target-ID field (in the buffer address 64 bit field) */
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#define AL_UDMA_DESC_TGTID_SHIFT 48
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2016-01-26 15:22:04 +00:00
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/** UDMA completion descriptor */
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union al_udma_cdesc {
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/* TX completion */
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struct {
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uint32_t ctrl_meta;
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} al_desc_comp_tx;
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/* RX completion */
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struct {
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/* TBD */
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uint32_t ctrl_meta;
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} al_desc_comp_rx;
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} __packed_a4;
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/* TX/RX common completion desc ctrl_meta feilds */
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#define AL_UDMA_CDESC_ERROR AL_BIT(31)
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#define AL_UDMA_CDESC_BUF1_USED AL_BIT(30)
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#define AL_UDMA_CDESC_DDP AL_BIT(29)
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#define AL_UDMA_CDESC_LAST AL_BIT(27)
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#define AL_UDMA_CDESC_FIRST AL_BIT(26)
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/* word 2 */
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#define AL_UDMA_CDESC_BUF2_USED AL_BIT(31)
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#define AL_UDMA_CDESC_BUF2_LEN_SHIFT 16
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#define AL_UDMA_CDESC_BUF2_LEN_MASK AL_FIELD_MASK(29, 16)
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/** Basic Buffer structure */
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struct al_buf {
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al_phys_addr_t addr; /**< Buffer physical address */
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uint32_t len; /**< Buffer lenght in bytes */
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};
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/** Block is a set of buffers that belong to same source or destination */
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struct al_block {
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struct al_buf *bufs; /**< The buffers of the block */
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uint32_t num; /**< Number of buffers of the block */
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/**<
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2016-09-06 14:59:13 +00:00
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* Target-ID to be assigned to the block descriptors
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* Requires Target-ID in descriptor to be enabled for the specific UDMA
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2016-01-26 15:22:04 +00:00
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* queue.
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*/
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2016-09-06 14:59:13 +00:00
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uint16_t tgtid;
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2016-01-26 15:22:04 +00:00
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};
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/** UDMA type */
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enum al_udma_type {
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UDMA_TX,
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UDMA_RX
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};
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/** UDMA state */
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enum al_udma_state {
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UDMA_DISABLE = 0,
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UDMA_IDLE,
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UDMA_NORMAL,
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UDMA_ABORT,
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UDMA_RESET
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};
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extern const char *const al_udma_states_name[];
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/** UDMA Q specific parameters from upper layer */
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struct al_udma_q_params {
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uint32_t size; /**< ring size (in descriptors), submission and
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* completion rings must have same size
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*/
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union al_udma_desc *desc_base; /**< cpu address for submission ring
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* descriptors
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*/
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al_phys_addr_t desc_phy_base; /**< submission ring descriptors
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* physical base address
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*/
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#ifdef __FreeBSD__
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bus_dma_tag_t desc_phy_base_tag;
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bus_dmamap_t desc_phy_base_map;
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#endif
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uint8_t *cdesc_base; /**< completion descriptors pointer, NULL */
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/* means no completion update */
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al_phys_addr_t cdesc_phy_base; /**< completion descriptors ring
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* physical base address
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*/
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#ifdef __FreeBSD__
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bus_dma_tag_t cdesc_phy_base_tag;
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bus_dmamap_t cdesc_phy_base_map;
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#endif
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uint32_t cdesc_size; /**< size (in bytes) of a single dma completion
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* descriptor
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*/
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uint8_t adapter_rev_id; /**<PCI adapter revision ID */
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};
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/** UDMA parameters from upper layer */
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struct al_udma_params {
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struct unit_regs __iomem *udma_regs_base;
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enum al_udma_type type; /**< Tx or Rx */
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uint8_t num_of_queues; /**< number of queues supported by the UDMA */
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const char *name; /**< the upper layer must keep the string area */
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};
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/* Fordward decleration */
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struct al_udma;
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/** SW status of a queue */
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enum al_udma_queue_status {
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AL_QUEUE_NOT_INITIALIZED = 0,
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AL_QUEUE_DISABLED,
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AL_QUEUE_ENABLED,
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AL_QUEUE_ABORTED
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};
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/** UDMA Queue private data structure */
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struct __cache_aligned al_udma_q {
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uint16_t size_mask; /**< mask used for pointers wrap around
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* equals to size - 1
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*/
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union udma_q_regs __iomem *q_regs; /**< pointer to the per queue UDMA
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* registers
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*/
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union al_udma_desc *desc_base_ptr; /**< base address submission ring
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* descriptors
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*/
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uint16_t next_desc_idx; /**< index to the next available submission
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* descriptor
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*/
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uint32_t desc_ring_id; /**< current submission ring id */
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uint8_t *cdesc_base_ptr;/**< completion descriptors pointer, NULL */
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/* means no completion */
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uint32_t cdesc_size; /**< size (in bytes) of the udma completion ring
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* descriptor
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*/
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uint16_t next_cdesc_idx; /**< index in descriptors for next completing
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* ring descriptor
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*/
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uint8_t *end_cdesc_ptr; /**< used for wrap around detection */
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uint16_t comp_head_idx; /**< completion ring head pointer register
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*shadow
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*/
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volatile union al_udma_cdesc *comp_head_ptr; /**< when working in get_packet mode
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* we maintain pointer instead of the
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* above idx
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*/
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uint32_t pkt_crnt_descs; /**< holds the number of processed descriptors
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* of the current packet
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*/
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uint32_t comp_ring_id; /**< current completion Ring Id */
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al_phys_addr_t desc_phy_base; /**< submission desc. physical base */
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al_phys_addr_t cdesc_phy_base; /**< completion desc. physical base */
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uint32_t flags; /**< flags used for completion modes */
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uint32_t size; /**< ring size in descriptors */
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enum al_udma_queue_status status;
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struct al_udma *udma; /**< pointer to parent UDMA */
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uint32_t qid; /**< the index number of the queue */
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/*
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* The following fields are duplicated from the UDMA parent adapter
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* due to performance considerations.
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*/
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uint8_t adapter_rev_id; /**<PCI adapter revision ID */
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};
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/* UDMA */
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struct al_udma {
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const char *name;
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enum al_udma_type type; /* Tx or Rx */
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enum al_udma_state state;
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uint8_t num_of_queues; /* number of queues supported by the UDMA */
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union udma_regs __iomem *udma_regs; /* pointer to the UDMA registers */
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struct udma_gen_regs *gen_regs; /* pointer to the Gen registers*/
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struct al_udma_q udma_q[DMA_MAX_Q]; /* Array of UDMA Qs pointers */
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unsigned int rev_id; /* UDMA revision ID */
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};
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/*
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* Configurations
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*/
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/* Initializations functions */
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/**
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* Initialize the udma engine
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*
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* @param udma udma data structure
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* @param udma_params udma parameters from upper layer
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*
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* @return 0 on success. -EINVAL otherwise.
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*/
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int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params);
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/**
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* Initialize the udma queue data structure
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*
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* @param udma
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* @param qid
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* @param q_params
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*
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* @return 0 if no error found.
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* -EINVAL if the qid is out of range
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* -EIO if queue was already initialized
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*/
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int al_udma_q_init(struct al_udma *udma, uint32_t qid,
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struct al_udma_q_params *q_params);
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/**
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* Reset a udma queue
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*
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* Prior to calling this function make sure:
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* 1. Queue interrupts are masked
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* 2. No additional descriptors are written to the descriptor ring of the queue
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* 3. No completed descriptors are being fetched
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*
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* The queue can be initialized again using 'al_udma_q_init'
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*
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* @param udma_q
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*
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* @return 0 if no error found.
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*/
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int al_udma_q_reset(struct al_udma_q *udma_q);
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/**
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* return (by reference) a pointer to a specific queue date structure.
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|
|
|
* this pointer needed for calling functions (i.e. al_udma_desc_action_add) that
|
|
|
|
* require this pointer as input argument.
|
|
|
|
*
|
|
|
|
* @param udma udma data structure
|
|
|
|
* @param qid queue index
|
|
|
|
* @param q_handle pointer to the location where the queue structure pointer
|
|
|
|
* written to.
|
|
|
|
*
|
|
|
|
* @return 0 on success. -EINVAL otherwise.
|
|
|
|
*/
|
|
|
|
int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
|
|
|
|
struct al_udma_q **q_handle);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Change the UDMA's state
|
|
|
|
*
|
|
|
|
* @param udma udma data structure
|
|
|
|
* @param state the target state
|
|
|
|
*
|
|
|
|
* @return 0
|
|
|
|
*/
|
|
|
|
int al_udma_state_set(struct al_udma *udma, enum al_udma_state state);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* return the current UDMA hardware state
|
|
|
|
*
|
|
|
|
* @param udma udma handle
|
|
|
|
*
|
|
|
|
* @return the UDMA state as reported by the hardware.
|
|
|
|
*/
|
|
|
|
enum al_udma_state al_udma_state_get(struct al_udma *udma);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Action handling
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* get number of descriptors that can be submitted to the udma.
|
|
|
|
* keep one free descriptor to simplify full/empty management
|
|
|
|
* @param udma_q queue handle
|
|
|
|
*
|
|
|
|
* @return num of free descriptors.
|
|
|
|
*/
|
|
|
|
static INLINE uint32_t al_udma_available_get(struct al_udma_q *udma_q)
|
|
|
|
{
|
|
|
|
uint16_t tmp = udma_q->next_cdesc_idx - (udma_q->next_desc_idx + 1);
|
|
|
|
tmp &= udma_q->size_mask;
|
|
|
|
|
|
|
|
return (uint32_t) tmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* check if queue has pending descriptors
|
|
|
|
*
|
|
|
|
* @param udma_q queue handle
|
|
|
|
*
|
|
|
|
* @return AL_TRUE if descriptors are submitted to completion ring and still
|
|
|
|
* not completed (with ack). AL_FALSE otherwise.
|
|
|
|
*/
|
|
|
|
static INLINE al_bool al_udma_is_empty(struct al_udma_q *udma_q)
|
|
|
|
{
|
|
|
|
if (((udma_q->next_cdesc_idx - udma_q->next_desc_idx) &
|
|
|
|
udma_q->size_mask) == 0)
|
|
|
|
return AL_TRUE;
|
|
|
|
|
|
|
|
return AL_FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* get next available descriptor
|
|
|
|
* @param udma_q queue handle
|
|
|
|
*
|
|
|
|
* @return pointer to the next available descriptor
|
|
|
|
*/
|
|
|
|
static INLINE union al_udma_desc *al_udma_desc_get(struct al_udma_q *udma_q)
|
|
|
|
{
|
|
|
|
union al_udma_desc *desc;
|
|
|
|
uint16_t next_desc_idx;
|
|
|
|
|
|
|
|
al_assert(udma_q);
|
|
|
|
|
|
|
|
next_desc_idx = udma_q->next_desc_idx;
|
|
|
|
desc = udma_q->desc_base_ptr + next_desc_idx;
|
|
|
|
|
|
|
|
next_desc_idx++;
|
|
|
|
|
|
|
|
/* if reached end of queue, wrap around */
|
|
|
|
udma_q->next_desc_idx = next_desc_idx & udma_q->size_mask;
|
|
|
|
|
|
|
|
return desc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* get ring id for the last allocated descriptor
|
|
|
|
* @param udma_q
|
|
|
|
*
|
|
|
|
* @return ring id for the last allocated descriptor
|
|
|
|
* this function must be called each time a new descriptor is allocated
|
|
|
|
* by the al_udma_desc_get(), unless ring id is ignored.
|
|
|
|
*/
|
|
|
|
static INLINE uint32_t al_udma_ring_id_get(struct al_udma_q *udma_q)
|
|
|
|
{
|
|
|
|
uint32_t ring_id;
|
|
|
|
|
|
|
|
al_assert(udma_q);
|
|
|
|
|
|
|
|
ring_id = udma_q->desc_ring_id;
|
|
|
|
|
|
|
|
/* calculate the ring id of the next desc */
|
|
|
|
/* if next_desc points to first desc, then queue wrapped around */
|
|
|
|
if (unlikely(udma_q->next_desc_idx) == 0)
|
|
|
|
udma_q->desc_ring_id = (udma_q->desc_ring_id + 1) &
|
|
|
|
DMA_RING_ID_MASK;
|
|
|
|
return ring_id;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add DMA action - trigger the engine */
|
|
|
|
/**
|
|
|
|
* add num descriptors to the submission queue.
|
|
|
|
*
|
|
|
|
* @param udma_q queue handle
|
|
|
|
* @param num number of descriptors to add to the queues ring.
|
|
|
|
*
|
|
|
|
* @return 0;
|
|
|
|
*/
|
|
|
|
static INLINE int al_udma_desc_action_add(struct al_udma_q *udma_q,
|
|
|
|
uint32_t num)
|
|
|
|
{
|
|
|
|
uint32_t *addr;
|
|
|
|
|
|
|
|
al_assert(udma_q);
|
|
|
|
al_assert((num > 0) && (num <= udma_q->size));
|
|
|
|
|
|
|
|
addr = &udma_q->q_regs->rings.drtp_inc;
|
|
|
|
/* make sure data written to the descriptors will be visible by the */
|
|
|
|
/* DMA */
|
|
|
|
al_local_data_memory_barrier();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* As we explicitly invoke the synchronization function
|
|
|
|
* (al_data_memory_barrier()), then we can use the relaxed version.
|
|
|
|
*/
|
|
|
|
al_reg_write32_relaxed(addr, num);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define cdesc_is_first(flags) ((flags) & AL_UDMA_CDESC_FIRST)
|
|
|
|
#define cdesc_is_last(flags) ((flags) & AL_UDMA_CDESC_LAST)
|
|
|
|
|
|
|
|
/**
|
|
|
|
* return pointer to the cdesc + offset desciptors. wrap around when needed.
|
|
|
|
*
|
|
|
|
* @param udma_q queue handle
|
|
|
|
* @param cdesc pointer that set by this function
|
|
|
|
* @param offset offset desciptors
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static INLINE volatile union al_udma_cdesc *al_cdesc_next(
|
|
|
|
struct al_udma_q *udma_q,
|
|
|
|
volatile union al_udma_cdesc *cdesc,
|
|
|
|
uint32_t offset)
|
|
|
|
{
|
|
|
|
volatile uint8_t *tmp = (volatile uint8_t *) cdesc + offset * udma_q->cdesc_size;
|
|
|
|
al_assert(udma_q);
|
|
|
|
al_assert(cdesc);
|
|
|
|
|
|
|
|
/* if wrap around */
|
|
|
|
if (unlikely((tmp > udma_q->end_cdesc_ptr)))
|
|
|
|
return (union al_udma_cdesc *)
|
|
|
|
(udma_q->cdesc_base_ptr +
|
|
|
|
(tmp - udma_q->end_cdesc_ptr - udma_q->cdesc_size));
|
|
|
|
|
|
|
|
return (volatile union al_udma_cdesc *) tmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* check if the flags of the descriptor indicates that is new one
|
|
|
|
* the function uses the ring id from the descriptor flags to know whether it
|
|
|
|
* new one by comparing it with the curring ring id of the queue
|
|
|
|
*
|
|
|
|
* @param udma_q queue handle
|
|
|
|
* @param flags the flags of the completion descriptor
|
|
|
|
*
|
|
|
|
* @return AL_TRUE if the completion descriptor is new one.
|
|
|
|
* AL_FALSE if it old one.
|
|
|
|
*/
|
|
|
|
static INLINE al_bool al_udma_new_cdesc(struct al_udma_q *udma_q,
|
|
|
|
uint32_t flags)
|
|
|
|
{
|
|
|
|
if (((flags & AL_M2S_DESC_RING_ID_MASK) >> AL_M2S_DESC_RING_ID_SHIFT)
|
|
|
|
== udma_q->comp_ring_id)
|
|
|
|
return AL_TRUE;
|
|
|
|
return AL_FALSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* get next completion descriptor
|
|
|
|
* this function will also increment the completion ring id when the ring wraps
|
|
|
|
* around
|
|
|
|
*
|
|
|
|
* @param udma_q queue handle
|
|
|
|
* @param cdesc current completion descriptor
|
|
|
|
*
|
|
|
|
* @return pointer to the completion descriptor that follows the one pointed by
|
|
|
|
* cdesc
|
|
|
|
*/
|
|
|
|
static INLINE volatile union al_udma_cdesc *al_cdesc_next_update(
|
|
|
|
struct al_udma_q *udma_q,
|
|
|
|
volatile union al_udma_cdesc *cdesc)
|
|
|
|
{
|
|
|
|
/* if last desc, wrap around */
|
|
|
|
if (unlikely(((volatile uint8_t *) cdesc == udma_q->end_cdesc_ptr))) {
|
|
|
|
udma_q->comp_ring_id =
|
|
|
|
(udma_q->comp_ring_id + 1) & DMA_RING_ID_MASK;
|
|
|
|
return (union al_udma_cdesc *) udma_q->cdesc_base_ptr;
|
|
|
|
}
|
|
|
|
return (volatile union al_udma_cdesc *) ((volatile uint8_t *) cdesc + udma_q->cdesc_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* get next completed packet from completion ring of the queue
|
|
|
|
*
|
|
|
|
* @param udma_q udma queue handle
|
|
|
|
* @param desc pointer that set by this function to the first descriptor
|
|
|
|
* note: desc is valid only when return value is not zero
|
|
|
|
* @return number of descriptors that belong to the packet. 0 means no completed
|
|
|
|
* full packet was found.
|
|
|
|
* If the descriptors found in the completion queue don't form full packet (no
|
|
|
|
* desc with LAST flag), then this function will do the following:
|
|
|
|
* (1) save the number of processed descriptors.
|
|
|
|
* (2) save last processed descriptor, so next time it called, it will resume
|
|
|
|
* from there.
|
|
|
|
* (3) return 0.
|
|
|
|
* note: the descriptors that belong to the completed packet will still be
|
|
|
|
* considered as used, that means the upper layer is safe to access those
|
|
|
|
* descriptors when this function returns. the al_udma_cdesc_ack() should be
|
|
|
|
* called to inform the udma driver that those descriptors are freed.
|
|
|
|
*/
|
|
|
|
uint32_t al_udma_cdesc_packet_get(
|
|
|
|
struct al_udma_q *udma_q,
|
|
|
|
volatile union al_udma_cdesc **desc);
|
|
|
|
|
|
|
|
/** get completion descriptor pointer from its index */
|
|
|
|
#define al_udma_cdesc_idx_to_ptr(udma_q, idx) \
|
|
|
|
((volatile union al_udma_cdesc *) ((udma_q)->cdesc_base_ptr + \
|
|
|
|
(idx) * (udma_q)->cdesc_size))
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
* return number of all completed descriptors in the completion ring
|
|
|
|
*
|
|
|
|
* @param udma_q udma queue handle
|
|
|
|
* @param cdesc pointer that set by this function to the first descriptor
|
|
|
|
* note: desc is valid only when return value is not zero
|
|
|
|
* note: pass NULL if not interested
|
|
|
|
* @return number of descriptors. 0 means no completed descriptors were found.
|
|
|
|
* note: the descriptors that belong to the completed packet will still be
|
|
|
|
* considered as used, that means the upper layer is safe to access those
|
|
|
|
* descriptors when this function returns. the al_udma_cdesc_ack() should be
|
|
|
|
* called to inform the udma driver that those descriptors are freed.
|
|
|
|
*/
|
|
|
|
static INLINE uint32_t al_udma_cdesc_get_all(
|
|
|
|
struct al_udma_q *udma_q,
|
|
|
|
volatile union al_udma_cdesc **cdesc)
|
|
|
|
{
|
|
|
|
uint16_t count = 0;
|
|
|
|
|
|
|
|
al_assert(udma_q);
|
|
|
|
|
|
|
|
udma_q->comp_head_idx = (uint16_t)
|
|
|
|
(al_reg_read32(&udma_q->q_regs->rings.crhp) &
|
|
|
|
0xFFFF);
|
|
|
|
|
|
|
|
count = (udma_q->comp_head_idx - udma_q->next_cdesc_idx) &
|
|
|
|
udma_q->size_mask;
|
|
|
|
|
|
|
|
if (cdesc)
|
|
|
|
*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
|
|
|
|
|
|
|
|
return (uint32_t)count;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* acknowledge the driver that the upper layer completed processing completion
|
|
|
|
* descriptors
|
|
|
|
*
|
|
|
|
* @param udma_q udma queue handle
|
|
|
|
* @param num number of descriptors to acknowledge
|
|
|
|
*
|
|
|
|
* @return 0
|
|
|
|
*/
|
|
|
|
static INLINE int al_udma_cdesc_ack(struct al_udma_q *udma_q, uint32_t num)
|
|
|
|
{
|
|
|
|
al_assert(udma_q);
|
|
|
|
|
|
|
|
udma_q->next_cdesc_idx += num;
|
|
|
|
udma_q->next_cdesc_idx &= udma_q->size_mask;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* *INDENT-OFF* */
|
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/* *INDENT-ON* */
|
|
|
|
|
|
|
|
#endif /* __AL_HAL_UDMA_H__ */
|
|
|
|
/** @} end of UDMA group */
|