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freebsd-skq/sys/mips/nlm/mpreset.S

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Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
/*-
* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
* reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
*
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
* NETLOGIC_BSD
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* $FreeBSD$
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
*/
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include <mips/nlm/hal/iomap.h>
#include <mips/nlm/hal/sys.h>
#include <mips/nlm/hal/cpucontrol.h>
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
#define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \
XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4)
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
#include "assym.s"
.text
.set noat
.set noreorder
.set mips64
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
#define MFCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x18))
#define MTCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x19))
/*
* We need to do this to really flush the dcache before splitting it
*/
.macro flush_l1_dcache
.set push
.set noreorder
li $8, LSU_DEBUG_DATA0 /* use register number to handle */
li $9, LSU_DEBUG_ADDR /* different ABIs */
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
li t2, 0 /* index */
li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
1:
sll v0, t2, 5
MTCR(0, 8)
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
ori v1, v0, 0x3 /* way0 | write_enable | write_active */
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
MTCR(3, 9)
2:
MFCR(3, 9)
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
andi v1, 0x1 /* wait for write_active == 0 */
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
bnez v1, 2b
nop
MTCR(0, 8)
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
ori v1, v0, 0x7 /* way1 | write_enable | write_active */
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
MTCR(3, 9)
3:
MFCR(3, 9)
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
andi v1, 0x1 /* wait for write_active == 0 */
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
bnez v1, 3b
nop
addi t2, 1
bne t3, t2, 1b
nop
.set pop
.endm
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
VECTOR(XLPResetEntry, unknown)
mfc0 t0, MIPS_COP_0_STATUS
li t1, 0x80000
and t1, t0, t1
bnez t1, nmi_handler
nop
#ifdef SMP
/* Reset entry for secordary cores */
mfc0 t0, MIPS_COP_0_PRID, 1
srl t0, t0, 2 /* discard thread id */
andi t0, t0, 0x7 /* core id */
li t1, 1
sll t0, t1, t0
nor t0, t0, zero /* mask with core id bit clear */
/* clear CPU non-coherent bit */
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
lw t1, 0(t2)
and t1, t1, t0
sw t1, 0(t2)
lw t1, 0(t2) /* read-back ensures operation complete */
sync
dla t2, mpentry
jr t2
nop
#endif
nop
/* NOT REACHED */
VECTOR_END(XLPResetEntry)
/* Not yet */
nmi_handler:
nop
nop
j nmi_handler
#ifdef SMP
/*
* Enable other threads in the core, called from thread 0
* of the core
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
*/
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
LEAF(xlp_enable_threads)
/*
* Save and restore callee saved registers of all ABIs
* Enabling threads trashes the registers
*/
dmtc0 sp, $4, 2 /* SP saved in UserLocal */
ori sp, sp, 0x7
xori sp, sp, 0x7 /* align 64 bit */
addiu sp, sp, -128
mfc0 t1, MIPS_COP_0_STATUS
sd s0, 0(sp)
sd s1, 8(sp)
sd s2, 16(sp)
sd s3, 24(sp)
sd s4, 32(sp)
sd s5, 40(sp)
sd s6, 48(sp)
sd s7, 56(sp)
sd s8, 64(sp)
sd t1, 72(sp)
sd gp, 80(sp)
sd ra, 88(sp)
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
flush_l1_dcache
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
/* Use register number to work in o32 and n32 */
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
move $8, a0
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
sync
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
MTCR(8, 9)
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
mfc0 t0, MIPS_COP_0_PRID, 1
andi t0, 0x3
beqz t0, 2f
nop
dla t1, mpentry /* child thread, go to hardware init */
jr t1
nop
Whitespace fixes for files in sys/mips/nlm Clean up whitespace issues under sys/mips/nlm (except dev). No functional change in this commit.
2015-02-28 00:17:29 +00:00
2: /*
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* Parent hardware thread, restore registers, return
*/
#if 1
/*
* A0 Errata - Write MMU_SETUP after changing thread mode register.
*/
li $9, 0x400
li $8, 0
Do dcache flush on CPU core before enabling threads. The dcache flush has to be done using the core control registers before splitting the L1D cache by enabling the hardware threads. Also replace .word calls for mfcr/mtcr with a C macro. In collaboration with: prabhath at netlogicmicro com
2011-11-21 16:43:24 +00:00
MTCR(8, 9)
sll zero,3 /* ehb */
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
#endif
dmfc0 t0, $4, 2 /* SP saved in UserLocal */
ori sp, t0, 0x7
xori sp, sp, 0x7 /* align 64 bit */
addiu sp, sp, -128
ld s0, 0(sp)
ld s1, 8(sp)
ld s2, 16(sp)
ld s3, 24(sp)
ld s4, 32(sp)
ld s5, 40(sp)
ld s6, 48(sp)
ld s7, 56(sp)
ld s8, 64(sp)
ld t1, 72(sp)
ld gp, 80(sp)
ld ra, 88(sp)
mfc0 t1, MIPS_COP_0_STATUS
move sp, t0 /* Restore the real SP */
Update the L1D cache flush sequence when enabling threads. Added more comments to the code.
2012-03-27 07:51:42 +00:00
jr.hb ra
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
nop
END(xlp_enable_threads)
#endif
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