2006-07-25 00:16:09 +00:00
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/*-
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* Copyright (c) 2006, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_IP1000PHYREG_H_
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#define _DEV_MII_IP1000PHYREG_H_
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/*
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* Registers for the IC Plus IP1000A internal PHY.
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*/
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/* Control register */
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#define IP1000PHY_MII_BMCR 0x00
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#define IP1000PHY_BMCR_FDX 0x0100
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#define IP1000PHY_BMCR_STARTNEG 0x0200
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#define IP1000PHY_BMCR_ISO 0x0400
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#define IP1000PHY_BMCR_PDOWN 0x0800
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#define IP1000PHY_BMCR_AUTOEN 0x1000
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#define IP1000PHY_BMCR_LOOP 0x4000
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#define IP1000PHY_BMCR_RESET 0x8000
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#define IP1000PHY_BMCR_10 0x0000
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#define IP1000PHY_BMCR_100 0x2000
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#define IP1000PHY_BMCR_1000 0x0040
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/* Status register */
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#define IP1000PHY_MII_BMSR 0x01
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#define IP1000PHY_BMSR_EXT 0x0001
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#define IP1000PHY_BMSR_LINK 0x0004
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#define IP1000PHY_BMSR_ANEG 0x0008
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#define IP1000PHY_BMSR_RFAULT 0x0010
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#define IP1000PHY_BMSR_ANEGCOMP 0x0020
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#define IP1000PHY_BMSR_EXTSTS 0x0100
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#define IP1000PHY_MII_ID1 0x02
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/* Autonegotiation advertisement register */
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#define IP1000PHY_MII_ANAR 0x04
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2009-03-09 08:17:46 +00:00
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#define IP1000PHY_ANAR_CSMA 0x0001
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2006-07-25 00:16:09 +00:00
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#define IP1000PHY_ANAR_10T 0x0020
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#define IP1000PHY_ANAR_10T_FDX 0x0040
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#define IP1000PHY_ANAR_100TX 0x0080
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#define IP1000PHY_ANAR_100TX_FDX 0x0100
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#define IP1000PHY_ANAR_100T4 0x0200
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#define IP1000PHY_ANAR_PAUSE 0x0400
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#define IP1000PHY_ANAR_APAUSE 0x0800
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#define IP1000PHY_ANAR_RFAULT 0x2000
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#define IP1000PHY_ANAR_NP 0x8000
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/* Autonegotiation link parnet ability register */
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#define IP1000PHY_MII_ANLPAR 0x05
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#define IP1000PHY_ANLPAR_10T 0x0020
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#define IP1000PHY_ANLPAR_10T_FDX 0x0040
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#define IP1000PHY_ANLPAR_100TX 0x0080
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#define IP1000PHY_ANLPAR_100TX_FDX 0x0100
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#define IP1000PHY_ANLPAR_100T4 0x0200
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#define IP1000PHY_ANLPAR_PAUSE 0x0400
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#define IP1000PHY_ANLPAR_APAUSE 0x0800
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#define IP1000PHY_ANLPAR_RFAULT 0x2000
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#define IP1000PHY_ANLPAR_ACK 0x4000
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#define IP1000PHY_ANLPAR_NP 0x8000
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/* Autonegotiation expansion register */
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#define IP1000PHY_MII_ANER 0x06
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#define IP1000PHY_ANER_LPNWAY 0x0001
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#define IP1000PHY_ANER_PRCVD 0x0002
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#define IP1000PHY_ANER_NEXTP 0x0004
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#define IP1000PHY_ANER_LPNEXTP 0x0008
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#define IP1000PHY_ANER_PDF 0x0100
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/* Autonegotiation next page transmit register */
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#define IP1000PHY_MII_NEXTP 0x07
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#define IP1000PHY_NEXTP_MSGC 0x0001
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#define IP1000PHY_NEXTP_TOGGLE 0x0800
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#define IP1000PHY_NEXTP_ACK2 0x1000
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#define IP1000PHY_NEXTP_MSGP 0x2000
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#define IP1000PHY_NEXTP_NEXTP 0x8000
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/* Autonegotiation link partner next page register */
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#define IP1000PHY_MII_NEXTPLP 0x08
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#define IP1000PHY_NEXTPLP_MSGC 0x0001
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#define IP1000PHY_NEXTPLP_TOGGLE 0x0800
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#define IP1000PHY_NEXTPLP_ACK2 0x1000
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#define IP1000PHY_NEXTPLP_MSGP 0x2000
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#define IP1000PHY_NEXTPLP_ACK 0x4000
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#define IP1000PHY_NEXTPLP_NEXTP 0x8000
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/* 1000baseT control register */
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#define IP1000PHY_MII_1000CR 0x09
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#define IP1000PHY_1000CR_1000T 0x0100
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#define IP1000PHY_1000CR_1000T_FDX 0x0200
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#define IP1000PHY_1000CR_MASTER 0x0400
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#define IP1000PHY_1000CR_MMASTER 0x0800
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#define IP1000PHY_1000CR_MANUAL 0x1000
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#define IP1000PHY_1000CR_TMNORMAL 0x0000
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#define IP1000PHY_1000CR_TM1 0x2000
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#define IP1000PHY_1000CR_TM2 0x4000
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#define IP1000PHY_1000CR_TM3 0x6000
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#define IP1000PHY_1000CR_TM4 0x8000
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/* 1000baseT status register */
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#define IP1000PHY_MII_1000SR 0x0A
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#define IP1000PHY_1000SR_LP 0x0400
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#define IP1000PHY_1000SR_LP_FDX 0x0800
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#define IP1000PHY_1000SR_RXSTAT 0x1000
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#define IP1000PHY_1000SR_LRXSTAT 0x2000
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#define IP1000PHY_1000SR_MASTER 0x4000
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#define IP1000PHY_1000SR_MASTERF 0x8000
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/* Extended status register */
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#define IP1000PHY_MII_EXTSTS 0x0F
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#define IP1000PHY_EXTSTS_1000T 0x1000
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#define IP1000PHY_EXTSTS_1000T_FDX 0x2000
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#define IP1000PHY_EXTSTS_1000X 0x4000
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#define IP1000PHY_EXTSTS_1000X_FDX 0x8000
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2008-04-05 00:52:07 +00:00
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/* PHY specific control & status register. IP1001 only. */
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#define IP1000PHY_SCSR 0x10
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#define IP1000PHY_SCSR_RXPHASE_SEL 0x0001
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#define IP1000PHY_SCSR_TXPHASE_SEL 0x0002
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#define IP1000PHY_SCSR_REPEATOR_MODE 0x0004
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#define IP1000PHY_SCSR_RESERVED1_DEF 0x0008
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#define IP1000PHY_SCSR_RXCLK_DRV_MASK 0x0060
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#define IP1000PHY_SCSR_RXCLK_DRV_DEF 0x0040
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#define IP1000PHY_SCSR_RXD_DRV_MASK 0x0180
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#define IP1000PHY_SCSR_RXD_DRV_DEF 0x0100
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#define IP1000PHY_SCSR_JABBER_ENB 0x0200
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#define IP1000PHY_SCSR_HEART_BEAT_ENB 0x0400
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#define IP1000PHY_SCSR_DOWNSHIFT_ENB 0x0800
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#define IP1000PHY_SCSR_RESERVED2_DEF 0x1000
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#define IP1000PHY_SCSR_LED_DRV_4MA 0x0000
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#define IP1000PHY_SCSR_LED_DRV_8MA 0x2000
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#define IP1000PHY_SCSR_LED_MODE_MASK 0xC000
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#define IP1000PHY_SCSR_LED_MODE_DEF 0x0000
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/* PHY link status register. IP1001 only. */
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#define IP1000PHY_LSR 0x11
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#define IP1000PHY_LSR_JABBER_DET 0x0200
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#define IP1000PHY_LSR_APS_SLEEP 0x0400
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#define IP1000PHY_LSR_MDIX 0x0800
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#define IP1000PHY_LSR_FULL_DUPLEX 0x1000
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#define IP1000PHY_LSR_SPEED_10 0x0000
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#define IP1000PHY_LSR_SPEED_100 0x2000
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#define IP1000PHY_LSR_SPEED_1000 0x4000
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#define IP1000PHY_LSR_SPEED_MASK 0x6000
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#define IP1000PHY_LSR_LINKUP 0x8000
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/* PHY specific control register 2. IP1001 only. */
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#define IP1000PHY_SCR
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#define IP1000PHY_SCR_SEW_RATE_MASK 0x0003
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#define IP1000PHY_SCR_SEW_RATE_DEF 0x0003
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#define IP1000PHY_SCR_AUTO_XOVER 0x0004
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#define IP1000PHY_SCR_SPEED_10_100_ENB 0x0040
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#define IP1000PHY_SCR_FIFO_LATENCY_2 0x0000
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#define IP1000PHY_SCR_FIFO_LATENCY_3 0x0080
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#define IP1000PHY_SCR_FIFO_LATENCY_4 0x0100
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#define IP1000PHY_SCR_FIFO_LATENCY_5 0x0180
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#define IP1000PHY_SCR_MDIX_ENB 0x0200
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#define IP1000PHY_SCR_RESERVED_DEF 0x0400
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#define IP1000PHY_SCR_APS_ON 0x0800
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2006-07-25 00:16:09 +00:00
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#endif /* _DEV_MII_IP1000PHYREG_H_ */
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