2010-07-20 07:11:19 +00:00
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/***********************license start***************
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2012-03-11 04:14:00 +00:00
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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2010-11-28 06:20:41 +00:00
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* reserved.
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2010-07-20 07:11:19 +00:00
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*
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*
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2010-11-28 06:20:41 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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2010-07-20 07:11:19 +00:00
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*
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2010-11-28 06:20:41 +00:00
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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2010-07-20 07:11:19 +00:00
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*
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2010-11-28 06:20:41 +00:00
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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2012-03-11 04:14:00 +00:00
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* * Neither the name of Cavium Inc. nor the names of
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2010-11-28 06:20:41 +00:00
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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2012-03-11 04:14:00 +00:00
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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2010-11-28 06:20:41 +00:00
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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2010-07-20 07:11:19 +00:00
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***********************license end**************************************/
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2010-11-28 06:20:41 +00:00
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2010-07-20 07:11:19 +00:00
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/**
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* @file
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*
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* Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
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* XAUI.
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*
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2012-03-11 04:14:00 +00:00
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* <hr>$Revision: 70030 $<hr>
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2010-07-20 07:11:19 +00:00
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*/
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#ifndef __CVMX_HIGIG_H__
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#define __CVMX_HIGIG_H__
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#include "cvmx-wqe.h"
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2012-03-11 04:14:00 +00:00
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#include "cvmx-helper.h"
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#include "cvmx-helper-util.h"
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2010-07-20 07:11:19 +00:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct
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{
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */
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uint32_t hgi : 2; /**< HiGig interface format indicator
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00 = Reserved
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01 = Pure preamble - IEEE standard framing of 10GE
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10 = XGS header - framing based on XGS family definition In this
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format, the default length of the header is 12 bytes and additional
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bytes are indicated by the HDR_EXT_LEN field
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11 = Reserved */
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2012-03-11 04:14:00 +00:00
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uint32_t cng_high : 1; /**< Congestion Bit High flag */
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uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
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to the standard 12-bytes of XGS HiGig header. Each unit represents 4
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bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
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and b'111' are reserved. For HGI field value of b'01' this field should be
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b'01'. For all other values of HGI it is don't care. */
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uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
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SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
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value of b'01' this field should be b'0'. For all other values of HGI it is don't
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care. */
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uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
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DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
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value of b'01' this field should be b'1'. For all other values of HGI it is don't
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care. */
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2010-07-20 07:11:19 +00:00
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uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */
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uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */
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} s;
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} dw0;
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union
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{
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uint32_t u32;
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struct
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{
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2012-03-11 04:14:00 +00:00
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uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
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5 is in Byte 9 and bit 6 Is in Byte 1) */
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2010-07-20 07:11:19 +00:00
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uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet
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000 = Control frames used for CPU to CPU communications
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001 = Unicast packet with destination resolved; The packet can be
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either Layer 2 unicast packet or L3 unicast packet that was
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routed in the ingress chip.
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010 = Broadcast or unknown Unicast packet or unknown multicast,
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destined to all members of the VLAN
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011 = L2 Multicast packet, destined to all ports of the group indicated
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in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
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100 = IP Multicast packet, destined to all ports of the group indicated
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in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
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101 = Reserved
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110 = Reserved
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111 = Reserved */
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uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
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multicast (unknown L2 multicast and IPMC) packets. This field is used
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when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
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For registered L2 multicast packets:
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PFM= 0 <EFBFBD> Flood to VLAN
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PFM= 1 or 2 <EFBFBD> Send to group members in the L2MC table
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For unregistered L2 multicast packets:
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PFM= 0 or 1 <EFBFBD> Flood to VLAN
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PFM= 2 <EFBFBD> Drop the packet */
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2012-03-11 04:14:00 +00:00
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uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
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on, else it represents the physical port the packet ingressed on. */
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uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */
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2010-07-20 07:11:19 +00:00
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uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through
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COS_SEL mapping registers to map to the actual MMU queues. */
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2012-03-11 04:14:00 +00:00
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uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
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00 = Overlay 1 (default)
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01 = Overlay 2 (Classification Tag)
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10 = Reserved
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11 = Reserved */
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2010-07-20 07:11:19 +00:00
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uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
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encodings are to make it backward compatible:
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2012-03-11 04:14:00 +00:00
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[CNG_HIGH, CNG_LOW] - COLOR
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2010-07-20 07:11:19 +00:00
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[0, 0] <EFBFBD> Packet is green
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[0, 1] <EFBFBD> Packet is red
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[1, 1] <EFBFBD> Packet is yellow
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[1, 0] <EFBFBD> Undefined */
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2012-03-11 04:14:00 +00:00
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uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
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2010-07-20 07:11:19 +00:00
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} s;
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} dw1;
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
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group. */
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2012-03-11 04:14:00 +00:00
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uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
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DO_NOT_LEARN bit is overlaid on the second bit of this field. */
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uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
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ingressed the system. */
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uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
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needs to be mirrored. */
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uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
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may still need to be switched. */
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uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
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packet was switched and only needs to be mirrored. */
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2010-07-20 07:11:19 +00:00
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uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in
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byte 1) */
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2012-03-11 04:14:00 +00:00
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uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
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is in byte 1) */
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uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */
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uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
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added field. */
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uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
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2010-07-20 07:11:19 +00:00
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uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */
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} o1;
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struct
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{
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uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
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uint32_t reserved_0_15 : 16;
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} o2;
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} dw2;
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} cvmx_higig_header_t;
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2010-11-28 06:20:41 +00:00
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typedef struct
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{
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t k_sop : 8; /**< The delimiter indicating the start of a packet transmission */
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uint32_t reserved_21_23 : 3;
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uint32_t mcst : 1; /**< MCST indicates whether the packet should be unicast or
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multicast forwarded through the XGS switching fabric
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- 0: Unicast
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- 1: Mulitcast */
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uint32_t tc : 4; /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS)
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the switching fabric will provide when forwarding the packet
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through the fabric */
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uint32_t dst_modid_mgid : 8; /**< When MCST=0, this field indicates the destination XGS module to
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which the packet will be delivered. When MCST=1, this field indicates
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higher order bits of the Multicast Group ID. */
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uint32_t dst_pid_mgid : 8; /**< When MCST=0, this field indicates a port associated with the
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module indicated by the DST_MODID, through which the packet
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will exit the system. When MCST=1, this field indicates lower order
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bits of the Multicast Group ID */
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} s;
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} dw0;
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t src_modid : 8; /**< Source Module ID indicates the source XGS module from which
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the packet is originated. (It can also be used for the fabric multicast
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load balancing purpose.) */
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uint32_t src_pid : 8; /**< Source Port ID indicates a port associated with the module
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indicated by the SRC_MODID, through which the packet has
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entered the system */
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uint32_t lbid : 8; /**< Load Balancing ID indicates a packet flow hashing index
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computed by the ingress XGS module for statistical distribution of
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packet flows through a multipath fabric */
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uint32_t dp : 2; /**< Drop Precedence indicates the traffic rate violation status of the
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packet measured by the ingress module.
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- 00: GREEN
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- 01: RED
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- 10: Reserved
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- 11: Yellow */
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uint32_t reserved_3_5 : 3;
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uint32_t ppd_type : 3; /**< Packet Processing Descriptor Type
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- 000: PPD Overlay1
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- 001: PPD Overlay2
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- 010~111: Reserved */
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} s;
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} dw1;
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union
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{
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uint32_t u32;
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struct
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{
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uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
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group. */
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uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
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|
DO_NOT_LEARN bit is overlaid on the second bit of this field. */
|
|
|
|
|
|
uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
|
|
|
|
|
|
ingressed the system. */
|
|
|
|
|
|
uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
|
|
|
|
|
|
needs to be mirrored. */
|
|
|
|
|
|
uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
|
|
|
|
|
|
may still need to be switched. */
|
|
|
|
|
|
uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
|
|
|
|
|
|
packet was switched and only needs to be mirrored. */
|
|
|
|
|
|
uint32_t reserved_22_23 : 2;
|
|
|
|
|
|
uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */
|
|
|
|
|
|
uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
|
|
|
|
|
|
added field. */
|
|
|
|
|
|
uint32_t vc_label : 20; /**< Refer to the HiGig+ Architecture Specification */
|
|
|
|
|
|
} o1;
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
|
|
|
|
|
|
uint32_t reserved_0_15 : 16;
|
|
|
|
|
|
} o2;
|
|
|
|
|
|
} dw2;
|
|
|
|
|
|
union
|
|
|
|
|
|
{
|
|
|
|
|
|
uint32_t u32;
|
|
|
|
|
|
struct
|
|
|
|
|
|
{
|
|
|
|
|
|
uint32_t vid : 16; /**< VLAN tag information */
|
|
|
|
|
|
uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
|
|
|
|
|
|
multicast (unknown L2 multicast and IPMC) packets. This field is used
|
|
|
|
|
|
when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
|
|
|
|
|
|
For registered L2 multicast packets:
|
|
|
|
|
|
PFM= 0 <EFBFBD> Flood to VLAN
|
|
|
|
|
|
PFM= 1 or 2 <EFBFBD> Send to group members in the L2MC table
|
|
|
|
|
|
For unregistered L2 multicast packets:
|
|
|
|
|
|
PFM= 0 or 1 <EFBFBD> Flood to VLAN
|
|
|
|
|
|
PFM= 2 <EFBFBD> Drop the packet */
|
|
|
|
|
|
uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
|
|
|
|
|
|
on, else it represents the physical port the packet ingressed on. */
|
|
|
|
|
|
uint32_t reserved_11_12 : 2;
|
|
|
|
|
|
uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet
|
|
|
|
|
|
000 = Control frames used for CPU to CPU communications
|
|
|
|
|
|
001 = Unicast packet with destination resolved; The packet can be
|
|
|
|
|
|
either Layer 2 unicast packet or L3 unicast packet that was
|
|
|
|
|
|
routed in the ingress chip.
|
|
|
|
|
|
010 = Broadcast or unknown Unicast packet or unknown multicast,
|
|
|
|
|
|
destined to all members of the VLAN
|
|
|
|
|
|
011 = L2 Multicast packet, destined to all ports of the group indicated
|
|
|
|
|
|
in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
|
|
|
|
|
|
100 = IP Multicast packet, destined to all ports of the group indicated
|
|
|
|
|
|
in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
|
|
|
|
|
|
101 = Reserved
|
|
|
|
|
|
110 = Reserved
|
|
|
|
|
|
111 = Reserved */
|
|
|
|
|
|
uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
|
|
|
|
|
|
to the standard 12-bytes of XGS HiGig header. Each unit represents 4
|
|
|
|
|
|
bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
|
|
|
|
|
|
and b'111' are reserved. For HGI field value of b'01' this field should be
|
|
|
|
|
|
b'01'. For all other values of HGI it is don't care. */
|
|
|
|
|
|
uint32_t reserved_0_4 : 5;
|
|
|
|
|
|
} s;
|
|
|
|
|
|
} dw3;
|
|
|
|
|
|
} cvmx_higig2_header_t;
|
|
|
|
|
|
|
2010-07-20 07:11:19 +00:00
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
|
* Initialize the HiGig aspects of a XAUI interface. This function
|
|
|
|
|
|
* should be called before the cvmx-helper generic init.
|
|
|
|
|
|
*
|
|
|
|
|
|
* @param interface Interface to initialize HiGig on (0-1)
|
|
|
|
|
|
* @param enable_higig2
|
|
|
|
|
|
* Non zero to enable HiGig2 support. Zero to support HiGig
|
|
|
|
|
|
* and HiGig+.
|
|
|
|
|
|
*
|
|
|
|
|
|
* @return Zero on success, negative on failure
|
|
|
|
|
|
*/
|
|
|
|
|
|
static inline int cvmx_higig_initialize(int interface, int enable_higig2)
|
|
|
|
|
|
{
|
|
|
|
|
|
cvmx_pip_prt_cfgx_t pip_prt_cfg;
|
|
|
|
|
|
cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp;
|
|
|
|
|
|
cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt;
|
|
|
|
|
|
cvmx_gmxx_txx_append_t gmx_tx_append;
|
|
|
|
|
|
cvmx_gmxx_tx_ifg_t gmx_tx_ifg;
|
|
|
|
|
|
cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
|
|
|
|
|
|
cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl;
|
|
|
|
|
|
cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl;
|
2012-03-11 04:14:00 +00:00
|
|
|
|
int i, pknd;
|
2010-07-20 07:11:19 +00:00
|
|
|
|
int header_size = (enable_higig2) ? 16 : 12;
|
|
|
|
|
|
|
|
|
|
|
|
/* Setup PIP to handle HiGig */
|
2012-03-11 04:14:00 +00:00
|
|
|
|
if (octeon_has_feature(OCTEON_FEATURE_PKND))
|
|
|
|
|
|
pknd = cvmx_helper_get_pknd(interface, 0);
|
|
|
|
|
|
else
|
|
|
|
|
|
pknd = interface*16;
|
|
|
|
|
|
pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(pknd));
|
2010-07-20 07:11:19 +00:00
|
|
|
|
pip_prt_cfg.s.dsa_en = 0;
|
|
|
|
|
|
pip_prt_cfg.s.higig_en = 1;
|
|
|
|
|
|
pip_prt_cfg.s.hg_qos = 1;
|
|
|
|
|
|
pip_prt_cfg.s.skip = header_size;
|
2012-03-11 04:14:00 +00:00
|
|
|
|
cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64);
|
2010-07-20 07:11:19 +00:00
|
|
|
|
|
|
|
|
|
|
/* Setup some sample QoS defaults. These can be changed later */
|
2012-03-11 04:14:00 +00:00
|
|
|
|
if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
|
2010-07-20 07:11:19 +00:00
|
|
|
|
{
|
2012-03-11 04:14:00 +00:00
|
|
|
|
for (i=0; i<64; i++)
|
|
|
|
|
|
{
|
|
|
|
|
|
cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
|
|
|
|
|
|
pip_hg_pri_qos.u64 = 0;
|
|
|
|
|
|
pip_hg_pri_qos.s.up_qos = 1;
|
|
|
|
|
|
pip_hg_pri_qos.s.pri = i;
|
|
|
|
|
|
pip_hg_pri_qos.s.qos = i&7;
|
|
|
|
|
|
cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
|
|
|
|
|
|
}
|
2010-07-20 07:11:19 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Setup GMX RX to treat the HiGig header as user data to ignore */
|
|
|
|
|
|
gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface));
|
|
|
|
|
|
gmx_rx_udd_skp.s.len = header_size;
|
|
|
|
|
|
gmx_rx_udd_skp.s.fcssel = 0;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64);
|
|
|
|
|
|
|
|
|
|
|
|
/* Disable GMX preamble checking */
|
|
|
|
|
|
gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface));
|
|
|
|
|
|
gmx_rx_frm_ctl.s.pre_chk = 0;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64);
|
|
|
|
|
|
|
|
|
|
|
|
/* Setup GMX TX to pad properly min sized packets */
|
|
|
|
|
|
gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface));
|
|
|
|
|
|
gmx_tx_min_pkt.s.min_size = 59 + header_size;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64);
|
|
|
|
|
|
|
|
|
|
|
|
/* Setup GMX TX to not add a preamble */
|
|
|
|
|
|
gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
|
|
|
|
|
|
gmx_tx_append.s.preamble = 0;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64);
|
|
|
|
|
|
|
|
|
|
|
|
/* Reduce the inter frame gap to 8 bytes */
|
|
|
|
|
|
gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface));
|
|
|
|
|
|
gmx_tx_ifg.s.ifg1 = 4;
|
|
|
|
|
|
gmx_tx_ifg.s.ifg2 = 4;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64);
|
|
|
|
|
|
|
|
|
|
|
|
/* Disable GMX backpressure */
|
|
|
|
|
|
gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
|
|
|
|
|
|
gmx_tx_ovr_bp.s.bp = 0;
|
|
|
|
|
|
gmx_tx_ovr_bp.s.en = 0xf;
|
|
|
|
|
|
gmx_tx_ovr_bp.s.ign_full = 0xf;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
|
|
|
|
|
|
|
|
|
|
|
|
if (enable_higig2)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* Enable HiGig2 support and forwarding of virtual port backpressure
|
|
|
|
|
|
to PKO */
|
|
|
|
|
|
cvmx_gmxx_hg2_control_t gmx_hg2_control;
|
|
|
|
|
|
gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
|
|
|
|
|
|
gmx_hg2_control.s.hg2rx_en = 1;
|
|
|
|
|
|
gmx_hg2_control.s.hg2tx_en = 1;
|
|
|
|
|
|
gmx_hg2_control.s.logl_en = 0xffff;
|
|
|
|
|
|
gmx_hg2_control.s.phys_en = 1;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* Enable HiGig */
|
|
|
|
|
|
gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
|
|
|
|
|
|
gmx_tx_xaui_ctl.s.hg_en = 1;
|
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64);
|
|
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
|
}
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
#endif // __CVMX_HIGIG_H__
|
