d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
bce584a511
freebsd-skq/sys/arm/include/vm.h

57 lines
2.2 KiB
C
Raw Normal View History

This change is the next step in implementing the cache control functionality required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb
2009-06-26 04:47:43 +00:00
/*-
* Copyright (c) 2009 Alan L. Cox <alc@cs.rice.edu>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_VM_H_
#define _MACHINE_VM_H_
ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and dual implementation is showstopper for major cleanup. This patch only removes old code from tree. Cleanups will follow asap.
2016-01-29 10:31:54 +00:00
#include <machine/acle-compat.h>
#if __ARM_ARCH >= 6
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it. This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
#include <machine/pte-v6.h>
ARM: create new memory attribute for writethrough cacheable memory. - add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor)
2015-11-30 17:09:25 +00:00
#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA)
#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE)
#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE)
#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO)
ARM: Rename ARM specific VM_MEMATTR_WT memory attribute to standard one.
2016-01-31 09:16:20 +00:00
#define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)PTE2_ATTR_WT)
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it. This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
ARM: create new memory attribute for writethrough cacheable memory. - add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor)
2015-11-30 17:09:25 +00:00
#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA
#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */
ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and dual implementation is showstopper for major cleanup. This patch only removes old code from tree. Cleanups will follow asap.
2016-01-29 10:31:54 +00:00
#ifdef _KERNEL
/* Don't export aliased VM_MEMATTR to userland */
ARM: Rename ARM specific VM_MEMATTR_WT memory attribute to standard one.
2016-01-31 09:16:20 +00:00
#define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WRITE_THROUGH /* for DRM */
ARM: create new memory attribute for writethrough cacheable memory. - add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor)
2015-11-30 17:09:25 +00:00
#define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */
ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and dual implementation is showstopper for major cleanup. This patch only removes old code from tree. Cleanups will follow asap.
2016-01-29 10:31:54 +00:00
#endif
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it. This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
#else
Properly implement pmap_[get|set]_memattr Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
2012-12-19 00:24:31 +00:00
/* Memory attribute configuration. */
Add support to the virtual memory system for configuring machine- dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib)
2009-07-12 23:31:20 +00:00
#define VM_MEMATTR_DEFAULT 0
Properly implement pmap_[get|set]_memattr Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org>
2012-12-19 00:24:31 +00:00
#define VM_MEMATTR_UNCACHEABLE 1
New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it. This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
#endif
This change is the next step in implementing the cache control functionality required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb
2009-06-26 04:47:43 +00:00
Correct the #endif comment. Noticed by: jmallett Approved by: re (kib)
2009-06-26 16:22:24 +00:00
#endif /* !_MACHINE_VM_H_ */
Reference in New Issue Copy Permalink