2008-05-16 18:46:30 +00:00
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/******************************************************************************
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2013-06-18 21:28:19 +00:00
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Copyright (c) 2001-2013, Intel Corporation
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2008-05-16 18:46:30 +00:00
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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2007-07-11 23:03:16 +00:00
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2008-11-26 23:41:18 +00:00
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2007-07-11 23:03:16 +00:00
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#ifndef _IXGBE_H_
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#define _IXGBE_H_
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#include <sys/param.h>
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#include <sys/systm.h>
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2012-11-30 23:13:56 +00:00
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#ifndef IXGBE_LEGACY_TX
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2009-06-24 18:27:07 +00:00
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#include <sys/buf_ring.h>
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#endif
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2007-07-11 23:03:16 +00:00
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#include <sys/mbuf.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sockio.h>
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2013-10-26 17:58:36 +00:00
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#include <sys/eventhandler.h>
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2007-07-11 23:03:16 +00:00
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#include <net/if.h>
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2013-10-26 17:58:36 +00:00
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#include <net/if_var.h>
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2007-07-11 23:03:16 +00:00
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#include <net/if_arp.h>
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#include <net/bpf.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/bpf.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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2009-04-10 00:22:48 +00:00
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#include <netinet/tcp_lro.h>
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2007-07-11 23:03:16 +00:00
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#include <netinet/udp.h>
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#include <machine/in_cksum.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/clock.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <sys/proc.h>
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#include <sys/sysctl.h>
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#include <sys/endian.h>
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#include <sys/taskqueue.h>
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2008-05-16 18:46:30 +00:00
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#include <sys/pcpu.h>
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2009-06-24 18:27:07 +00:00
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#include <sys/smp.h>
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#include <machine/smp.h>
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2007-07-11 23:03:16 +00:00
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#include "ixgbe_api.h"
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/* Tunables */
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/*
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2007-09-04 02:31:35 +00:00
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* TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
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2007-07-11 23:03:16 +00:00
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* number of transmit descriptors allocated by the driver. Increasing this
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* value allows the driver to queue more transmits. Each descriptor is 16
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2007-09-04 02:31:35 +00:00
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* bytes. Performance tests have show the 2K value to be optimal for top
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* performance.
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2007-07-11 23:03:16 +00:00
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*/
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2009-04-10 00:22:48 +00:00
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#define DEFAULT_TXD 1024
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2007-09-04 02:31:35 +00:00
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#define PERFORM_TXD 2048
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2007-07-11 23:03:16 +00:00
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#define MAX_TXD 4096
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#define MIN_TXD 64
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/*
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2007-09-04 02:31:35 +00:00
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* RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
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* number of receive descriptors allocated for each RX queue. Increasing this
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2007-07-11 23:03:16 +00:00
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* value allows the driver to buffer more incoming packets. Each descriptor
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2007-09-04 02:31:35 +00:00
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* is 16 bytes. A receive buffer is also allocated for each descriptor.
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2007-07-11 23:03:16 +00:00
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*
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2007-09-04 02:31:35 +00:00
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* Note: with 8 rings and a dual port card, it is possible to bump up
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* against the system mbuf pool limit, you can tune nmbclusters
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* to adjust for this.
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2007-07-11 23:03:16 +00:00
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*/
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2009-04-10 00:22:48 +00:00
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#define DEFAULT_RXD 1024
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2007-09-04 02:31:35 +00:00
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#define PERFORM_RXD 2048
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2007-07-11 23:03:16 +00:00
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#define MAX_RXD 4096
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#define MIN_RXD 64
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2007-09-04 02:31:35 +00:00
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/* Alignment for rings */
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#define DBA_ALIGN 128
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2007-07-11 23:03:16 +00:00
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/*
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* This parameter controls the maximum no of times the driver will loop in
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* the isr. Minimum Value = 1
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*/
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2008-11-26 23:41:18 +00:00
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#define MAX_LOOP 10
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2007-07-11 23:03:16 +00:00
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/*
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2009-12-07 21:30:54 +00:00
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* This is the max watchdog interval, ie. the time that can
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* pass between any two TX clean operations, such only happening
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* when the TX hardware is functioning.
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2007-07-11 23:03:16 +00:00
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*/
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2009-12-07 21:30:54 +00:00
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#define IXGBE_WATCHDOG (10 * hz)
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2007-07-11 23:03:16 +00:00
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/*
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* This parameters control when the driver calls the routine to reclaim
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* transmit descriptors.
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*/
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#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
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#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
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#define IXGBE_MAX_FRAME_SIZE 0x3F00
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2007-09-04 02:31:35 +00:00
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/* Flow control constants */
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2009-12-07 21:30:54 +00:00
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#define IXGBE_FC_PAUSE 0xFFFF
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2007-09-04 02:31:35 +00:00
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#define IXGBE_FC_HI 0x20000
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#define IXGBE_FC_LO 0x10000
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2007-07-11 23:03:16 +00:00
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2012-08-31 10:07:38 +00:00
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/*
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* Used for optimizing small rx mbufs. Effort is made to keep the copy
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* small and aligned for the CPU L1 cache.
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*
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* MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
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* 32 byte alignment needed for the fast bcopy results in 8 bytes being
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* wasted. Getting 64 byte alignment, which _should_ be ideal for
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* modern Intel CPUs, results in 40 bytes wasted and a significant drop
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* in observed efficiency of the optimization, 97.9% -> 81.8%.
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*/
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2015-02-28 14:57:57 +00:00
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#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32)
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#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
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#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE)
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2012-08-31 10:07:38 +00:00
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2011-04-28 23:21:40 +00:00
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/* Keep older OS drivers building... */
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#if !defined(SYSCTL_ADD_UQUAD)
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#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
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#endif
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2007-07-11 23:03:16 +00:00
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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2009-04-10 00:22:48 +00:00
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#define IXGBE_82598_SCATTER 100
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#define IXGBE_82599_SCATTER 32
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2008-11-26 23:41:18 +00:00
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#define MSIX_82598_BAR 3
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#define MSIX_82599_BAR 4
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2012-04-23 22:05:09 +00:00
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#define IXGBE_TSO_SIZE 262140
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2007-07-11 23:03:16 +00:00
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#define IXGBE_TX_BUFFER_SIZE ((u32) 1514)
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2010-03-27 00:21:40 +00:00
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#define IXGBE_RX_HDR 128
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2009-06-24 18:27:07 +00:00
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#define IXGBE_VFTA_SIZE 128
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#define IXGBE_BR_SIZE 4096
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2012-01-30 16:42:02 +00:00
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#define IXGBE_QUEUE_MIN_FREE 32
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2010-03-30 19:09:18 +00:00
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/* Offload bits in mbuf flag */
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#if __FreeBSD_version >= 800000
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#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
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#else
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#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
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#endif
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2007-07-11 23:03:16 +00:00
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/*
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* Interrupt Moderation parameters
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*/
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2008-11-26 23:41:18 +00:00
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#define IXGBE_LOW_LATENCY 128
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#define IXGBE_AVE_LATENCY 400
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#define IXGBE_BULK_LATENCY 1200
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#define IXGBE_LINK_ITR 2000
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2013-06-18 21:28:19 +00:00
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2007-07-11 23:03:16 +00:00
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/*
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2008-11-26 23:41:18 +00:00
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*****************************************************************************
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2007-07-11 23:03:16 +00:00
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* vendor_info_array
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*
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* This array contains the list of Subvendor/Subdevice IDs on which the driver
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* should load.
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*
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2008-11-26 23:41:18 +00:00
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*****************************************************************************
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2007-07-11 23:03:16 +00:00
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*/
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typedef struct _ixgbe_vendor_info_t {
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unsigned int vendor_id;
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unsigned int device_id;
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unsigned int subvendor_id;
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unsigned int subdevice_id;
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unsigned int index;
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2008-11-26 23:41:18 +00:00
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} ixgbe_vendor_info_t;
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2007-07-11 23:03:16 +00:00
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struct ixgbe_tx_buf {
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2012-12-01 00:11:24 +00:00
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union ixgbe_adv_tx_desc *eop;
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2007-07-11 23:03:16 +00:00
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struct mbuf *m_head;
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bus_dmamap_t map;
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};
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struct ixgbe_rx_buf {
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2012-11-30 22:19:18 +00:00
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struct mbuf *buf;
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2010-03-27 00:21:40 +00:00
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struct mbuf *fmp;
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2012-12-20 22:26:03 +00:00
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bus_dmamap_t pmap;
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2012-08-31 10:07:38 +00:00
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u_int flags;
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#define IXGBE_RX_COPY 0x01
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2012-11-30 22:19:18 +00:00
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uint64_t addr;
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2007-07-11 23:03:16 +00:00
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};
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/*
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* Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free.
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*/
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struct ixgbe_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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bus_size_t dma_size;
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int dma_nseg;
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};
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/*
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2010-03-27 00:21:40 +00:00
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** Driver queue struct: this is the interrupt container
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** for the associated tx and rx ring.
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*/
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struct ix_queue {
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struct adapter *adapter;
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u32 msix; /* This queue's MSIX vector */
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u32 eims; /* This queue's EIMS bit */
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u32 eitr_setting;
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struct resource *res;
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void *tag;
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struct tx_ring *txr;
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struct rx_ring *rxr;
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struct task que_task;
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struct taskqueue *tq;
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u64 irqs;
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};
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/*
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* The transmit ring, one per queue
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2007-07-11 23:03:16 +00:00
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*/
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struct tx_ring {
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struct adapter *adapter;
|
2008-05-16 18:46:30 +00:00
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struct mtx tx_mtx;
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2007-07-11 23:03:16 +00:00
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u32 me;
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2012-11-30 23:45:55 +00:00
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int watchdog_time;
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union ixgbe_adv_tx_desc *tx_base;
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struct ixgbe_tx_buf *tx_buffers;
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struct ixgbe_dma_alloc txdma;
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volatile u16 tx_avail;
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u16 next_avail_desc;
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u16 next_to_clean;
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u16 process_limit;
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u16 num_desc;
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2012-11-30 22:33:21 +00:00
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enum {
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IXGBE_QUEUE_IDLE,
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IXGBE_QUEUE_WORKING,
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IXGBE_QUEUE_HUNG,
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} queue_status;
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2008-05-16 18:46:30 +00:00
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u32 txd_cmd;
|
2007-07-11 23:03:16 +00:00
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bus_dma_tag_t txtag;
|
2008-11-26 23:41:18 +00:00
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char mtx_name[16];
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2012-11-30 23:13:56 +00:00
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#ifndef IXGBE_LEGACY_TX
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2009-06-24 18:27:07 +00:00
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struct buf_ring *br;
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2012-09-26 18:11:43 +00:00
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struct task txq_task;
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2009-06-24 18:27:07 +00:00
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#endif
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2009-12-07 21:30:54 +00:00
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#ifdef IXGBE_FDIR
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u16 atr_sample;
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u16 atr_count;
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#endif
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2010-03-27 00:21:40 +00:00
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u32 bytes; /* used for AIM */
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u32 packets;
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2008-05-16 18:46:30 +00:00
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/* Soft Stats */
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2012-11-30 23:45:55 +00:00
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unsigned long tso_tx;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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2010-03-27 00:21:40 +00:00
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u64 no_desc_avail;
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2008-11-26 23:41:18 +00:00
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u64 total_packets;
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2007-07-11 23:03:16 +00:00
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};
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/*
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* The Receive ring, one per rx queue
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*/
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struct rx_ring {
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2008-05-16 18:46:30 +00:00
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struct adapter *adapter;
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struct mtx rx_mtx;
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u32 me;
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union ixgbe_adv_rx_desc *rx_base;
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struct ixgbe_dma_alloc rxdma;
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struct lro_ctrl lro;
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2009-06-24 18:27:07 +00:00
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bool lro_enabled;
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2009-12-07 21:30:54 +00:00
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bool hw_rsc;
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2012-01-30 16:42:02 +00:00
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bool vtag_strip;
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2012-11-30 23:45:55 +00:00
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u16 next_to_refresh;
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u16 next_to_check;
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u16 num_desc;
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u16 mbuf_sz;
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u16 process_limit;
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2010-03-27 00:21:40 +00:00
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char mtx_name[16];
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2008-05-16 18:46:30 +00:00
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struct ixgbe_rx_buf *rx_buffers;
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2012-12-20 22:26:03 +00:00
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bus_dma_tag_t ptag;
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2008-11-26 23:41:18 +00:00
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u32 bytes; /* Used for AIM calc */
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2010-03-27 00:21:40 +00:00
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u32 packets;
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2009-06-24 18:27:07 +00:00
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2007-07-11 23:03:16 +00:00
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/* Soft stats */
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2008-05-16 18:46:30 +00:00
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u64 rx_irq;
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2012-08-31 10:07:38 +00:00
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u64 rx_copies;
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2008-11-26 23:41:18 +00:00
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u64 rx_packets;
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u64 rx_bytes;
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2010-03-27 00:21:40 +00:00
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u64 rx_discarded;
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2009-12-07 21:30:54 +00:00
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u64 rsc_num;
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#ifdef IXGBE_FDIR
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u64 flm;
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#endif
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2007-07-11 23:03:16 +00:00
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};
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/* Our adapter structure */
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struct adapter {
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2010-03-27 00:21:40 +00:00
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struct ifnet *ifp;
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struct ixgbe_hw hw;
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2007-07-11 23:03:16 +00:00
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struct ixgbe_osdep osdep;
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2010-03-27 00:21:40 +00:00
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struct device *dev;
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2008-05-16 18:46:30 +00:00
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2010-03-27 00:21:40 +00:00
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struct resource *pci_mem;
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struct resource *msix_mem;
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2007-07-11 23:03:16 +00:00
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/*
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2009-06-24 18:27:07 +00:00
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* Interrupt resources: this set is
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* either used for legacy, or for Link
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* when doing MSIX
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2007-07-11 23:03:16 +00:00
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*/
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2010-03-27 00:21:40 +00:00
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void *tag;
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struct resource *res;
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2007-07-11 23:03:16 +00:00
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2010-03-27 00:21:40 +00:00
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struct ifmedia media;
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struct callout timer;
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int msix;
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int if_flags;
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2008-05-16 18:46:30 +00:00
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2010-03-27 00:21:40 +00:00
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struct mtx core_mtx;
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2008-05-16 18:46:30 +00:00
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2010-03-27 00:21:40 +00:00
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eventhandler_tag vlan_attach;
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eventhandler_tag vlan_detach;
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2009-06-24 18:27:07 +00:00
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2010-03-27 00:21:40 +00:00
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u16 num_vlans;
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u16 num_queues;
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2009-06-24 18:27:07 +00:00
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2010-11-26 22:46:32 +00:00
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/*
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** Shadow VFTA table, this is needed because
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** the real vlan filter table gets cleared during
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** a soft reset and the driver needs to be able
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** to repopulate it.
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*/
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u32 shadow_vfta[IXGBE_VFTA_SIZE];
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/* Info about the interface */
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2010-03-27 00:21:40 +00:00
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u32 optics;
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2012-01-30 16:42:02 +00:00
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u32 fc; /* local flow ctrl setting */
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2010-06-30 16:28:28 +00:00
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int advertise; /* link speeds */
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2010-03-27 00:21:40 +00:00
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bool link_active;
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u16 max_frame_size;
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2011-01-19 19:36:27 +00:00
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u16 num_segs;
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2010-03-27 00:21:40 +00:00
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u32 link_speed;
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bool link_up;
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u32 linkvec;
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2007-07-11 23:03:16 +00:00
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2008-11-26 23:41:18 +00:00
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/* Mbuf cluster size */
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2010-03-27 00:21:40 +00:00
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u32 rx_mbuf_sz;
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2008-11-26 23:41:18 +00:00
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2009-04-10 00:22:48 +00:00
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/* Support for pluggable optics */
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2010-03-27 00:21:40 +00:00
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bool sfp_probe;
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struct task link_task; /* Link tasklet */
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struct task mod_task; /* SFP tasklet */
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struct task msf_task; /* Multispeed Fiber */
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2009-12-07 21:30:54 +00:00
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#ifdef IXGBE_FDIR
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int fdir_reinit;
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struct task fdir_task;
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#endif
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2009-04-10 00:22:48 +00:00
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struct taskqueue *tq;
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2007-07-11 23:03:16 +00:00
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2010-03-27 00:21:40 +00:00
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/*
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** Queues:
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** This is the irq holder, it has
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** and RX/TX pair or rings associated
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** with it.
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*/
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struct ix_queue *queues;
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2007-07-11 23:03:16 +00:00
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/*
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* Transmit rings:
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* Allocated at run time, an array of rings.
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*/
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2010-03-27 00:21:40 +00:00
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struct tx_ring *tx_rings;
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2012-11-30 23:45:55 +00:00
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u32 num_tx_desc;
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2007-07-11 23:03:16 +00:00
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/*
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* Receive rings:
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* Allocated at run time, an array of rings.
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*/
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2010-03-27 00:21:40 +00:00
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struct rx_ring *rx_rings;
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u64 que_mask;
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2012-11-30 23:45:55 +00:00
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u32 num_rx_desc;
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2009-04-10 00:22:48 +00:00
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2010-11-27 00:00:33 +00:00
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/* Multicast array memory */
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u8 *mta;
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2013-06-18 21:28:19 +00:00
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2007-07-11 23:03:16 +00:00
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/* Misc stats maintained by the driver */
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2010-03-27 00:21:40 +00:00
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unsigned long dropped_pkts;
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unsigned long mbuf_defrag_failed;
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unsigned long mbuf_header_failed;
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unsigned long mbuf_packet_failed;
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unsigned long watchdog_events;
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unsigned long link_irq;
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struct ixgbe_hw_stats stats;
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2007-07-11 23:03:16 +00:00
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};
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2013-06-18 21:28:19 +00:00
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2009-04-10 00:22:48 +00:00
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/* Precision Time Sync (IEEE 1588) defines */
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#define ETHERTYPE_IEEE1588 0x88F7
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#define PICOSECS_PER_TICK 20833
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#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
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#define IXGBE_ADVTXD_TSTAMP 0x00080000
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2008-05-16 18:46:30 +00:00
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#define IXGBE_CORE_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF)
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#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
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2009-12-07 21:30:54 +00:00
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#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
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#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
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2008-05-16 18:46:30 +00:00
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#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
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2009-12-07 21:30:54 +00:00
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#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
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#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
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#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
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2008-05-16 18:46:30 +00:00
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#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
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#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
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#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
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#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
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#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
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2013-06-18 21:28:19 +00:00
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/* For backward compatibility */
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#if !defined(PCIER_LINK_STA)
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#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA
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#endif
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2008-05-16 18:46:30 +00:00
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2009-04-10 00:22:48 +00:00
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static inline bool
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ixgbe_is_sfp(struct ixgbe_hw *hw)
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{
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switch (hw->phy.type) {
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case ixgbe_phy_sfp_avago:
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case ixgbe_phy_sfp_ftl:
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case ixgbe_phy_sfp_intel:
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case ixgbe_phy_sfp_unknown:
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2010-03-27 00:21:40 +00:00
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case ixgbe_phy_sfp_passive_tyco:
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case ixgbe_phy_sfp_passive_unknown:
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2009-04-10 00:22:48 +00:00
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return TRUE;
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default:
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return FALSE;
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}
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}
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2010-06-03 00:00:45 +00:00
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/* Workaround to make 8.0 buildable */
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2011-01-07 22:58:12 +00:00
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#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
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2010-06-03 00:00:45 +00:00
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static __inline int
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drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
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{
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#ifdef ALTQ
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if (ALTQ_IS_ENABLED(&ifp->if_snd))
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return (1);
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#endif
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return (!buf_ring_empty(br));
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}
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#endif
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2011-04-25 23:34:21 +00:00
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/*
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** Find the number of unrefreshed RX descriptors
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*/
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static inline u16
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ixgbe_rx_unrefreshed(struct rx_ring *rxr)
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{
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if (rxr->next_to_check > rxr->next_to_refresh)
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return (rxr->next_to_check - rxr->next_to_refresh - 1);
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else
|
2012-11-30 23:45:55 +00:00
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return ((rxr->num_desc + rxr->next_to_check) -
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2011-04-25 23:34:21 +00:00
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rxr->next_to_refresh - 1);
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}
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2007-07-11 23:03:16 +00:00
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#endif /* _IXGBE_H_ */
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