202 lines
5.6 KiB
Plaintext
202 lines
5.6 KiB
Plaintext
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# The Archer C7 v2 is based on the AP135-020 board, with
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# TP-Link specific bits (eg flash layout, MAC address, etc.)
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# $FreeBSD$
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# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
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hint.qca955x_gmac.0.gmac_cfg=0x1
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# Use base mac address for wifi; +1 and +2 for arge0/arge1.
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hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00
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hint.ar71xx.0.eeprom_mac_isascii=0
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hint.ar71xx_mac_map.0.devid=ath
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hint.ar71xx_mac_map.0.unitid=0
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hint.ar71xx_mac_map.0.offset=0
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hint.ar71xx_mac_map.0.is_local=0
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hint.ar71xx_mac_map.1.devid=arge
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hint.ar71xx_mac_map.1.unitid=0
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hint.ar71xx_mac_map.1.offset=1
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hint.ar71xx_mac_map.1.is_local=0
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hint.ar71xx_mac_map.2.devid=arge
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hint.ar71xx_mac_map.2.unitid=1
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hint.ar71xx_mac_map.2.offset=2
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hint.ar71xx_mac_map.2.is_local=0
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# mdiobus0 on arge0
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hint.argemdio.0.at="nexus0"
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hint.argemdio.0.maddr=0x19000000
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hint.argemdio.0.msize=0x1000
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hint.argemdio.0.order=0
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# mdiobus1 on arge1 - required to bring up arge1?
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hint.argemdio.1.at="nexus0"
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hint.argemdio.1.maddr=0x1a000000
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hint.argemdio.1.msize=0x1000
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hint.argemdio.1.order=0
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# AR8327 - connected via mdiobus0 on arge0
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hint.arswitch.0.at="mdio0"
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hint.arswitch.0.is_7240=0 # definitely not the internal switch!
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hint.arswitch.0.is_9340=0 # not the internal switch!
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hint.arswitch.0.numphys=5 # all ports are PHYs
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hint.arswitch.0.phy4cpu=0
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hint.arswitch.0.is_rgmii=0 # not needed
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hint.arswitch.0.is_gmii=0 # not needed
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# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
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# The current code only supports one CPU port. So hm, what should
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# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
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# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
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# That's currently supposed to be hooked up to CPU port 0.
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# Other AR8327 configuration parameters
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# AP136-020 parameters
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# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
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# AR8327_PAD_MAC_SGMII
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hint.arswitch.0.pad.0.mode=3
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#hint.arswitch.0.pad.0.rxclk_delay_sel=0
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hint.arswitch.0.pad.0.sgmii_delay_en=1
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# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
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# AR8327_PAD_MAC_RGMII
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# XXX I think this hooks it up to the internal MAC6
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hint.arswitch.0.pad.6.mode=6
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hint.arswitch.0.pad.6.txclk_delay_en=1
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hint.arswitch.0.pad.6.rxclk_delay_en=1
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# AR8327_CLK_DELAY_SEL1
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hint.arswitch.0.pad.6.txclk_delay_sel=1
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# AR8327_CLK_DELAY_SEL2
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hint.arswitch.0.pad.6.rxclk_delay_sel=2
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# XXX there's no LED management just yet!
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hint.arswitch.0.led.ctrl0=0xc737c737
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hint.arswitch.0.led.ctrl1=0x00000000
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hint.arswitch.0.led.ctrl2=0x00000000
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hint.arswitch.0.led.ctrl3=0x00c30c00
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hint.arswitch.0.led.open_drain=0
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.0.force_link=1
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hint.arswitch.0.port.0.speed=1000
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hint.arswitch.0.port.0.duplex=1
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hint.arswitch.0.port.0.txpause=1
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hint.arswitch.0.port.0.rxpause=1
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.6.force_link=1
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hint.arswitch.0.port.6.speed=1000
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hint.arswitch.0.port.6.duplex=1
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hint.arswitch.0.port.6.txpause=1
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hint.arswitch.0.port.6.rxpause=1
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# arge0 - hooked up to AR8327 GMAC6, RGMII
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# set at 1000/full to the switch.
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# so, lock both sides of this connect up to 1000/full;
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# if_arge thus wont change the PLL configuration
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# upon a link status change.
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hint.arge.0.phymask=0x0
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hint.arge.0.miimode=3 # RGMII
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hint.arge.0.media=1000
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hint.arge.0.fduplex=1
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hint.arge.0.pll_1000=0x56000000
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# MAC for arge0 is the first 6 bytes of the ART
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hint.arge.0.eeprommac=0x1fff0000
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# arge1 - lock up to 1000/full
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hint.arge.1.phymask=0x0
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hint.arge.1.media=1000
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hint.arge.1.fduplex=1
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hint.arge.1.miimode=5 # SGMII
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hint.arge.1.pll_1000=0x03000101
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# MAC for arge1 is the second 6 bytes of the ART
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hint.arge.1.eeprommac=0x1fff0006
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# ath0: Where the ART is - last 64k in the flash
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hint.ath.0.eepromaddr=0x1fff0000
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hint.ath.0.eepromsize=16384
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# ath1: it's different; it's a PCIe attached device, so
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# we instead need to teach the PCIe bridge code about it
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# (ie, the 'early pci fixup' stuff that programs the PCIe
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# host registers on the NIC) and then we teach ath where
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# to find it.
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# ath1 hint - pcie slot 0
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# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
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# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
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# ath0 - eeprom comes from here
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# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
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# Flash layout - the tplink layout differs to what's passed
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# in via the kernel environment. What's passed in is based on
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# the AP135, but.. well, TP-Link.
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# 128 KiB u-boot
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hint.map.0.at="flash/spi0"
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hint.map.0.start=0x00000000
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hint.map.0.end=0x00020000 # 128k u-boot
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hint.map.0.name="u-boot"
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hint.map.0.readonly=1
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# Kernel
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hint.map.1.at="flash/spi0"
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hint.map.1.start=0x00020000
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hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
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hint.map.1.name="kernel"
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hint.map.1.readonly=1
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# Root
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hint.map.2.at="flash/spi0"
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hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
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hint.map.2.end=0x007d0000
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hint.map.2.name="rootfs"
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hint.map.2.readonly=1
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# 64KiB cfg
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hint.map.4.at="flash/spi0"
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hint.map.4.start=0x00fe0000
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hint.map.4.end=0x00ff0000
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hint.map.4.name="cfg"
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hint.map.4.readonly=0
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# 64KiB ART
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hint.map.6.at="flash/spi0"
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hint.map.6.start=0x00ff0000
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hint.map.6.end=0x01000000 # 64k ART
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hint.map.6.name="ART"
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hint.map.6.readonly=1
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# TODO: GPIO config
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# These are the GPIO LEDs and buttons which can be software controlled.
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hint.gpio.0.pinmask=0x00600000
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# Enable GPIO21, GPIO22 output and high - for USB power
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hint.gpio.0.pinon=0x00600000
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# TODO: GPIO pin config:
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# LED_WLAN2G 12
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# BTN_RFKILL 13
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# LED_SYSTEM 14
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# LED_QSS 15
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# BTN_RESET 16
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# LED_WLAN5G 17
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# LED_USB1 18
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# LED_USB2 19
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# USB2_POWER 21
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# USB1_POWER 22
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# TODO: PCIe isn't showing link; maybe uboot isn't initialising
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