1995-11-28 23:55:26 +00:00
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/*
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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1997-09-05 10:23:58 +00:00
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* Modifications to support NetBSD and media selection:
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* Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
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*
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1995-11-28 23:55:26 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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1999-08-28 01:08:13 +00:00
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* $FreeBSD$
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1995-11-28 23:55:26 +00:00
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*/
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/*
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1996-01-15 10:12:41 +00:00
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* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
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1995-11-28 23:55:26 +00:00
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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1996-10-12 19:49:43 +00:00
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#include <sys/socket.h>
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1995-11-28 23:55:26 +00:00
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#include <net/if.h>
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1997-09-29 11:27:43 +00:00
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#include <net/if_dl.h>
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1997-09-05 10:23:58 +00:00
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#include <net/if_media.h>
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1995-11-28 23:55:26 +00:00
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include <net/bpf.h>
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1997-09-05 10:23:58 +00:00
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#if defined(__NetBSD__)
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <net/if_dl.h>
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#include <net/if_ether.h>
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#include <netinet/if_inarp.h>
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#include <vm/vm.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/if_fxpreg.h>
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#include <dev/pci/if_fxpvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#else /* __FreeBSD__ */
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#include <sys/sockio.h>
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1999-04-16 21:22:55 +00:00
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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1997-09-05 10:23:58 +00:00
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1998-01-08 23:42:31 +00:00
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#include <net/ethernet.h>
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#include <net/if_arp.h>
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1997-09-05 10:23:58 +00:00
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1995-12-01 22:41:56 +00:00
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#include <vm/vm.h> /* for vtophys */
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1995-12-07 12:48:31 +00:00
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#include <vm/pmap.h> /* for vtophys */
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1995-12-01 22:41:56 +00:00
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#include <machine/clock.h> /* for DELAY */
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1995-11-28 23:55:26 +00:00
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#include <pci/pcivar.h>
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1999-03-20 04:51:25 +00:00
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#include <pci/pcireg.h> /* for PCIM_CMD_xxx */
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1995-11-28 23:55:26 +00:00
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#include <pci/if_fxpreg.h>
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1997-09-05 10:23:58 +00:00
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#include <pci/if_fxpvar.h>
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1995-11-28 23:55:26 +00:00
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1997-09-05 10:23:58 +00:00
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#endif /* __NetBSD__ */
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1995-11-28 23:55:26 +00:00
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1999-09-30 19:03:12 +00:00
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#ifdef __alpha__ /* XXX */
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/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
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#undef vtophys
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#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
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#endif /* __alpha__ */
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1999-03-17 16:44:53 +00:00
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#include "opt_bdg.h"
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#ifdef BRIDGE
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#include <net/if_types.h>
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#include <net/bridge.h>
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#endif
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1997-09-05 10:23:58 +00:00
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/*
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* NOTE! On the Alpha, we have an alignment constraint. The
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* card DMAs the packet immediately following the RFA. However,
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* the first thing in the packet is a 14-byte Ethernet header.
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* This means that the packet is misaligned. To compensate,
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* we actually offset the RFA 2 bytes into the cluster. This
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* alignes the packet after the Ethernet header at a 32-bit
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* boundary. HOWEVER! This means that the RFA is misaligned!
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*/
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#define RFA_ALIGNMENT_FUDGE 2
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/*
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* Inline function to copy a 16-bit aligned 32-bit quantity.
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*/
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static __inline void fxp_lwcopy __P((volatile u_int32_t *,
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volatile u_int32_t *));
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static __inline void
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fxp_lwcopy(src, dst)
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volatile u_int32_t *src, *dst;
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{
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1999-01-27 23:45:44 +00:00
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volatile u_int16_t *a = (volatile u_int16_t *)src;
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volatile u_int16_t *b = (volatile u_int16_t *)dst;
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1997-09-05 10:23:58 +00:00
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b[0] = a[0];
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b[1] = a[1];
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}
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1995-11-28 23:55:26 +00:00
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/*
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* Template for default configuration parameters.
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* See struct fxp_cb_config for the bit definitions.
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*/
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static u_char fxp_cb_config_template[] = {
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0x0, 0x0, /* cb_status */
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0x80, 0x2, /* cb_command */
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0xff, 0xff, 0xff, 0xff, /* link_addr */
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0x16, /* 0 */
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0x8, /* 1 */
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0x0, /* 2 */
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0x0, /* 3 */
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0x0, /* 4 */
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0x80, /* 5 */
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0xb2, /* 6 */
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0x3, /* 7 */
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0x1, /* 8 */
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0x0, /* 9 */
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0x26, /* 10 */
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0x0, /* 11 */
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0x60, /* 12 */
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0x0, /* 13 */
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0xf2, /* 14 */
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0x48, /* 15 */
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0x0, /* 16 */
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0x40, /* 17 */
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0xf3, /* 18 */
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0x0, /* 19 */
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0x3f, /* 20 */
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1997-09-29 11:27:43 +00:00
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0x5 /* 21 */
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1995-11-28 23:55:26 +00:00
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};
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1997-09-05 10:23:58 +00:00
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/* Supported media types. */
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struct fxp_supported_media {
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const int fsm_phy; /* PHY type */
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const int *fsm_media; /* the media array */
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const int fsm_nmedia; /* the number of supported media */
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const int fsm_defmedia; /* default media for this PHY */
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};
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1998-02-09 06:11:36 +00:00
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static const int fxp_media_standard[] = {
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1997-09-05 10:23:58 +00:00
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IFM_ETHER|IFM_10_T,
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IFM_ETHER|IFM_10_T|IFM_FDX,
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IFM_ETHER|IFM_100_TX,
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IFM_ETHER|IFM_100_TX|IFM_FDX,
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IFM_ETHER|IFM_AUTO,
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};
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#define FXP_MEDIA_STANDARD_DEFMEDIA (IFM_ETHER|IFM_AUTO)
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1998-02-09 06:11:36 +00:00
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static const int fxp_media_default[] = {
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1997-09-05 10:23:58 +00:00
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IFM_ETHER|IFM_MANUAL, /* XXX IFM_AUTO ? */
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};
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#define FXP_MEDIA_DEFAULT_DEFMEDIA (IFM_ETHER|IFM_MANUAL)
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1998-02-09 06:11:36 +00:00
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static const struct fxp_supported_media fxp_media[] = {
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1997-09-05 10:23:58 +00:00
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{ FXP_PHY_DP83840, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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{ FXP_PHY_DP83840A, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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1998-03-03 14:19:09 +00:00
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{ FXP_PHY_82553A, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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{ FXP_PHY_82553C, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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1997-09-05 10:23:58 +00:00
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{ FXP_PHY_82555, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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1998-03-03 14:19:09 +00:00
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{ FXP_PHY_82555B, fxp_media_standard,
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sizeof(fxp_media_standard) / sizeof(fxp_media_standard[0]),
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FXP_MEDIA_STANDARD_DEFMEDIA },
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1997-09-05 10:23:58 +00:00
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{ FXP_PHY_80C24, fxp_media_default,
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sizeof(fxp_media_default) / sizeof(fxp_media_default[0]),
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FXP_MEDIA_DEFAULT_DEFMEDIA },
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};
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#define NFXPMEDIA (sizeof(fxp_media) / sizeof(fxp_media[0]))
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static int fxp_mediachange __P((struct ifnet *));
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static void fxp_mediastatus __P((struct ifnet *, struct ifmediareq *));
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1998-04-15 17:47:40 +00:00
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static void fxp_set_media __P((struct fxp_softc *, int));
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static __inline void fxp_scb_wait __P((struct fxp_softc *));
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1997-09-05 10:23:58 +00:00
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static FXP_INTR_TYPE fxp_intr __P((void *));
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1995-11-28 23:55:26 +00:00
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static void fxp_start __P((struct ifnet *));
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1997-09-05 10:23:58 +00:00
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static int fxp_ioctl __P((struct ifnet *,
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1998-04-15 17:47:40 +00:00
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FXP_IOCTLCMD_TYPE, caddr_t));
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1996-12-10 07:29:50 +00:00
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static void fxp_init __P((void *));
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1995-12-05 02:01:59 +00:00
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static void fxp_stop __P((struct fxp_softc *));
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static void fxp_watchdog __P((struct ifnet *));
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1995-11-28 23:55:26 +00:00
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static int fxp_add_rfabuf __P((struct fxp_softc *, struct mbuf *));
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1997-09-05 10:23:58 +00:00
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static int fxp_mdi_read __P((struct fxp_softc *, int, int));
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static void fxp_mdi_write __P((struct fxp_softc *, int, int, int));
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2000-03-28 04:41:42 +00:00
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static void fxp_autosize_eeprom __P((struct fxp_softc *));
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1997-09-05 10:23:58 +00:00
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static void fxp_read_eeprom __P((struct fxp_softc *, u_int16_t *,
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1998-04-15 17:47:40 +00:00
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int, int));
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1997-09-05 10:23:58 +00:00
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static int fxp_attach_common __P((struct fxp_softc *, u_int8_t *));
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1998-02-09 06:11:36 +00:00
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static void fxp_stats_update __P((void *));
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1997-09-29 11:27:43 +00:00
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static void fxp_mc_setup __P((struct fxp_softc *));
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1995-11-28 23:55:26 +00:00
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1996-09-19 09:15:20 +00:00
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/*
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* Set initial transmit threshold at 64 (512 bytes). This is
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* increased by 64 (512 bytes) at a time, to maximum of 192
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* (1536 bytes), if an underrun occurs.
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*/
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static int tx_threshold = 64;
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1995-11-28 23:55:26 +00:00
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/*
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* Number of transmit control blocks. This determines the number
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* of transmit buffers that can be chained in the CB list.
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* This must be a power of two.
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*/
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1996-09-22 11:48:54 +00:00
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#define FXP_NTXCB 128
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1995-11-28 23:55:26 +00:00
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1998-08-04 08:53:12 +00:00
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/*
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* Number of completed TX commands at which point an interrupt
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* will be generated to garbage collect the attached buffers.
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* Must be at least one less than FXP_NTXCB, and should be
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* enough less so that the transmitter doesn't becomes idle
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* during the buffer rundown (which would reduce performance).
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*/
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#define FXP_CXINT_THRESH 120
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1995-11-28 23:55:26 +00:00
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/*
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* TxCB list index mask. This is used to do list wrap-around.
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*/
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#define FXP_TXCB_MASK (FXP_NTXCB - 1)
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/*
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* Number of receive frame area buffers. These are large so chose
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* wisely.
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*/
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1997-09-30 10:50:45 +00:00
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#define FXP_NRFABUFS 64
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1995-11-28 23:55:26 +00:00
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1997-09-29 11:27:43 +00:00
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/*
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* Maximum number of seconds that the receiver can be idle before we
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* assume it's dead and attempt to reset it by reprogramming the
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* multicast filter. This is part of a work-around for a bug in the
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* NIC. See fxp_stats_update().
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*/
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#define FXP_MAX_RX_IDLE 15
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1995-12-01 22:41:56 +00:00
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/*
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* Wait for the previous command to be accepted (but not necessarily
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* completed).
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*/
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1998-04-15 17:47:40 +00:00
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static __inline void
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1997-09-05 10:23:58 +00:00
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fxp_scb_wait(sc)
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struct fxp_softc *sc;
|
1995-11-28 23:55:26 +00:00
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{
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int i = 10000;
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1997-09-29 11:27:43 +00:00
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while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i);
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1995-11-28 23:55:26 +00:00
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}
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1997-09-05 10:23:58 +00:00
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/*************************************************************
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* Operating system-specific autoconfiguration glue
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*************************************************************/
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|
|
|
#if defined(__NetBSD__)
|
|
|
|
|
|
|
|
#ifdef __BROKEN_INDIRECT_CONFIG
|
|
|
|
static int fxp_match __P((struct device *, void *, void *));
|
|
|
|
#else
|
|
|
|
static int fxp_match __P((struct device *, struct cfdata *, void *));
|
|
|
|
#endif
|
|
|
|
static void fxp_attach __P((struct device *, struct device *, void *));
|
|
|
|
|
|
|
|
static void fxp_shutdown __P((void *));
|
|
|
|
|
|
|
|
/* Compensate for lack of a generic ether_ioctl() */
|
|
|
|
static int fxp_ether_ioctl __P((struct ifnet *,
|
|
|
|
FXP_IOCTLCMD_TYPE, caddr_t));
|
|
|
|
#define ether_ioctl fxp_ether_ioctl
|
|
|
|
|
|
|
|
struct cfattach fxp_ca = {
|
|
|
|
sizeof(struct fxp_softc), fxp_match, fxp_attach
|
|
|
|
};
|
|
|
|
|
|
|
|
struct cfdriver fxp_cd = {
|
|
|
|
NULL, "fxp", DV_IFNET
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if a device is an 82557.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
fxp_match(parent, match, aux)
|
|
|
|
struct device *parent;
|
|
|
|
#ifdef __BROKEN_INDIRECT_CONFIG
|
|
|
|
void *match;
|
|
|
|
#else
|
|
|
|
struct cfdata *match;
|
|
|
|
#endif
|
|
|
|
void *aux;
|
|
|
|
{
|
|
|
|
struct pci_attach_args *pa = aux;
|
|
|
|
|
|
|
|
if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL)
|
|
|
|
return (0);
|
|
|
|
|
|
|
|
switch (PCI_PRODUCT(pa->pa_id)) {
|
|
|
|
case PCI_PRODUCT_INTEL_82557:
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
fxp_attach(parent, self, aux)
|
|
|
|
struct device *parent, *self;
|
|
|
|
void *aux;
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = (struct fxp_softc *)self;
|
|
|
|
struct pci_attach_args *pa = aux;
|
|
|
|
pci_chipset_tag_t pc = pa->pa_pc;
|
|
|
|
pci_intr_handle_t ih;
|
|
|
|
const char *intrstr = NULL;
|
|
|
|
u_int8_t enaddr[6];
|
|
|
|
struct ifnet *ifp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map control/status registers.
|
|
|
|
*/
|
|
|
|
if (pci_mapreg_map(pa, FXP_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
|
|
|
|
&sc->sc_st, &sc->sc_sh, NULL, NULL)) {
|
|
|
|
printf(": can't map registers\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
printf(": Intel EtherExpress Pro 10/100B Ethernet\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate our interrupt.
|
|
|
|
*/
|
|
|
|
if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
|
|
|
|
pa->pa_intrline, &ih)) {
|
|
|
|
printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
intrstr = pci_intr_string(pc, ih);
|
|
|
|
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, fxp_intr, sc);
|
|
|
|
if (sc->sc_ih == NULL) {
|
|
|
|
printf("%s: couldn't establish interrupt",
|
|
|
|
sc->sc_dev.dv_xname);
|
|
|
|
if (intrstr != NULL)
|
|
|
|
printf(" at %s", intrstr);
|
|
|
|
printf("\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
|
|
|
|
|
|
|
|
/* Do generic parts of attach. */
|
|
|
|
if (fxp_attach_common(sc, enaddr)) {
|
|
|
|
/* Failed! */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("%s: Ethernet address %s%s\n", sc->sc_dev.dv_xname,
|
|
|
|
ether_sprintf(enaddr), sc->phy_10Mbps_only ? ", 10Mbps" : "");
|
|
|
|
|
|
|
|
ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
|
|
|
|
ifp->if_softc = sc;
|
|
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
|
|
ifp->if_ioctl = fxp_ioctl;
|
|
|
|
ifp->if_start = fxp_start;
|
|
|
|
ifp->if_watchdog = fxp_watchdog;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach the interface.
|
|
|
|
*/
|
|
|
|
if_attach(ifp);
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
1998-08-04 08:53:12 +00:00
|
|
|
* Let the system queue as many packets as we have available
|
|
|
|
* TX descriptors.
|
1997-10-23 01:45:15 +00:00
|
|
|
*/
|
1998-08-04 08:53:12 +00:00
|
|
|
ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
|
1997-09-05 10:23:58 +00:00
|
|
|
ether_ifattach(ifp, enaddr);
|
|
|
|
bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB,
|
|
|
|
sizeof(struct ether_header));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Add shutdown hook so that DMA is disabled prior to reboot. Not
|
|
|
|
* doing do could allow DMA to corrupt kernel memory during the
|
|
|
|
* reboot before the driver initializes.
|
|
|
|
*/
|
|
|
|
shutdownhook_establish(fxp_shutdown, sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device shutdown routine. Called at system shutdown after sync. The
|
|
|
|
* main purpose of this routine is to shut off receiver DMA so that
|
|
|
|
* kernel memory doesn't get clobbered during warmboot.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
fxp_shutdown(sc)
|
|
|
|
void *sc;
|
|
|
|
{
|
|
|
|
fxp_stop((struct fxp_softc *) sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
fxp_ether_ioctl(ifp, cmd, data)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
FXP_IOCTLCMD_TYPE cmd;
|
|
|
|
caddr_t data;
|
|
|
|
{
|
|
|
|
struct ifaddr *ifa = (struct ifaddr *) data;
|
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SIOCSIFADDR:
|
|
|
|
ifp->if_flags |= IFF_UP;
|
|
|
|
|
|
|
|
switch (ifa->ifa_addr->sa_family) {
|
|
|
|
#ifdef INET
|
|
|
|
case AF_INET:
|
|
|
|
fxp_init(sc);
|
|
|
|
arp_ifinit(ifp, ifa);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#ifdef NS
|
|
|
|
case AF_NS:
|
|
|
|
{
|
|
|
|
register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
|
|
|
|
|
|
|
|
if (ns_nullhost(*ina))
|
|
|
|
ina->x_host = *(union ns_host *)
|
|
|
|
LLADDR(ifp->if_sadl);
|
|
|
|
else
|
|
|
|
bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
|
|
|
|
ifp->if_addrlen);
|
|
|
|
/* Set new address. */
|
|
|
|
fxp_init(sc);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
fxp_init(sc);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* __FreeBSD__ */
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Return identification string if this is device is ours.
|
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
static int
|
|
|
|
fxp_probe(device_t dev)
|
1995-11-28 23:55:26 +00:00
|
|
|
{
|
1999-04-16 21:22:55 +00:00
|
|
|
if ((pci_get_vendor(dev) == FXP_VENDORID_INTEL) &&
|
|
|
|
(pci_get_device(dev) == FXP_DEVICEID_i82557)) {
|
|
|
|
device_set_desc(dev, "Intel EtherExpress Pro 10/100B Ethernet");
|
|
|
|
return 0;
|
|
|
|
}
|
1999-09-06 06:15:18 +00:00
|
|
|
if ((pci_get_vendor(dev) == FXP_VENDORID_INTEL) &&
|
|
|
|
(pci_get_device(dev) == FXP_DEVICEID_i82559)) {
|
|
|
|
device_set_desc(dev, "Intel InBusiness 10/100 Ethernet");
|
|
|
|
return 0;
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
return ENXIO;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
static int
|
|
|
|
fxp_attach(device_t dev)
|
1995-11-28 23:55:26 +00:00
|
|
|
{
|
1999-04-16 21:22:55 +00:00
|
|
|
int error = 0;
|
|
|
|
struct fxp_softc *sc = device_get_softc(dev);
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifnet *ifp;
|
|
|
|
int s;
|
1999-03-20 04:51:25 +00:00
|
|
|
u_long val;
|
1999-04-16 21:22:55 +00:00
|
|
|
int rid;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-21 22:02:25 +00:00
|
|
|
callout_handle_init(&sc->stat_ch);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
1999-03-20 04:51:25 +00:00
|
|
|
/*
|
|
|
|
* Enable bus mastering.
|
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
val = pci_read_config(dev, PCIR_COMMAND, 2);
|
1999-03-20 04:51:25 +00:00
|
|
|
val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
|
1999-04-16 21:22:55 +00:00
|
|
|
pci_write_config(dev, PCIR_COMMAND, val, 2);
|
1999-03-20 04:51:25 +00:00
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Map control/status registers.
|
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
rid = FXP_PCI_MMBA;
|
|
|
|
sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
0, ~0, 1, RF_ACTIVE);
|
|
|
|
if (!sc->mem) {
|
|
|
|
device_printf(dev, "could not map memory\n");
|
|
|
|
error = ENXIO;
|
1995-11-28 23:55:26 +00:00
|
|
|
goto fail;
|
1999-04-16 21:22:55 +00:00
|
|
|
}
|
1999-09-30 19:03:12 +00:00
|
|
|
|
|
|
|
sc->sc_st = rman_get_bustag(sc->mem);
|
|
|
|
sc->sc_sh = rman_get_bushandle(sc->mem);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Allocate our interrupt.
|
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
rid = 0;
|
|
|
|
sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
|
|
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
if (sc->irq == NULL) {
|
|
|
|
device_printf(dev, "could not map interrupt\n");
|
|
|
|
error = ENXIO;
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
1999-05-08 21:59:43 +00:00
|
|
|
error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
|
|
|
|
fxp_intr, sc, &sc->ih);
|
1999-04-16 21:22:55 +00:00
|
|
|
if (error) {
|
|
|
|
device_printf(dev, "could not setup irq\n");
|
1995-11-28 23:55:26 +00:00
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
/* Do generic parts of attach. */
|
|
|
|
if (fxp_attach_common(sc, sc->arpcom.ac_enaddr)) {
|
|
|
|
/* Failed! */
|
1999-04-16 21:22:55 +00:00
|
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
|
|
|
|
error = ENXIO;
|
1997-09-05 10:23:58 +00:00
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
device_printf(dev, "Ethernet address %6D%s\n",
|
1997-09-05 10:23:58 +00:00
|
|
|
sc->arpcom.ac_enaddr, ":", sc->phy_10Mbps_only ? ", 10Mbps" : "");
|
|
|
|
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
1999-04-16 21:22:55 +00:00
|
|
|
ifp->if_unit = device_get_unit(dev);
|
1997-09-05 10:23:58 +00:00
|
|
|
ifp->if_name = "fxp";
|
|
|
|
ifp->if_output = ether_output;
|
|
|
|
ifp->if_baudrate = 100000000;
|
|
|
|
ifp->if_init = fxp_init;
|
|
|
|
ifp->if_softc = sc;
|
|
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
|
|
ifp->if_ioctl = fxp_ioctl;
|
|
|
|
ifp->if_start = fxp_start;
|
|
|
|
ifp->if_watchdog = fxp_watchdog;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach the interface.
|
|
|
|
*/
|
|
|
|
if_attach(ifp);
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
1998-08-04 08:53:12 +00:00
|
|
|
* Let the system queue as many packets as we have available
|
|
|
|
* TX descriptors.
|
1997-10-23 01:45:15 +00:00
|
|
|
*/
|
1998-08-04 08:53:12 +00:00
|
|
|
ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
|
1997-09-05 10:23:58 +00:00
|
|
|
ether_ifattach(ifp);
|
|
|
|
bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
splx(s);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
splx(s);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Detach interface.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
fxp_detach(device_t dev)
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = device_get_softc(dev);
|
|
|
|
int s;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
/*
|
1999-04-16 21:22:55 +00:00
|
|
|
* Close down routes etc.
|
1997-09-05 10:23:58 +00:00
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
if_detach(&sc->arpcom.ac_if);
|
1997-09-05 10:23:58 +00:00
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
/*
|
|
|
|
* Stop DMA and drop transmit queue.
|
|
|
|
*/
|
|
|
|
fxp_stop(sc);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Deallocate resources.
|
|
|
|
*/
|
|
|
|
bus_teardown_intr(dev, sc->irq, sc->ih);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, FXP_PCI_MMBA, sc->mem);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free all the receive buffers.
|
|
|
|
*/
|
|
|
|
if (sc->rfa_headm != NULL)
|
|
|
|
m_freem(sc->rfa_headm);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free all media structures.
|
|
|
|
*/
|
|
|
|
ifmedia_removeall(&sc->sc_media);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free anciliary structures.
|
|
|
|
*/
|
|
|
|
free(sc->cbl_base, M_DEVBUF);
|
|
|
|
free(sc->fxp_stats, M_DEVBUF);
|
|
|
|
free(sc->mcsp, M_DEVBUF);
|
1997-09-05 10:23:58 +00:00
|
|
|
|
|
|
|
splx(s);
|
1999-04-16 21:22:55 +00:00
|
|
|
|
|
|
|
return 0;
|
1997-09-05 10:23:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device shutdown routine. Called at system shutdown after sync. The
|
|
|
|
* main purpose of this routine is to shut off receiver DMA so that
|
|
|
|
* kernel memory doesn't get clobbered during warmboot.
|
|
|
|
*/
|
1999-04-16 21:22:55 +00:00
|
|
|
static int
|
|
|
|
fxp_shutdown(device_t dev)
|
1997-09-05 10:23:58 +00:00
|
|
|
{
|
1999-04-16 21:22:55 +00:00
|
|
|
/*
|
|
|
|
* Make sure that DMA is disabled prior to reboot. Not doing
|
|
|
|
* do could allow DMA to corrupt kernel memory during the
|
|
|
|
* reboot before the driver initializes.
|
|
|
|
*/
|
|
|
|
fxp_stop((struct fxp_softc *) device_get_softc(dev));
|
|
|
|
return 0;
|
1997-09-05 10:23:58 +00:00
|
|
|
}
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
static device_method_t fxp_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, fxp_probe),
|
|
|
|
DEVMETHOD(device_attach, fxp_attach),
|
|
|
|
DEVMETHOD(device_detach, fxp_detach),
|
|
|
|
DEVMETHOD(device_shutdown, fxp_shutdown),
|
|
|
|
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t fxp_driver = {
|
|
|
|
"fxp",
|
|
|
|
fxp_methods,
|
|
|
|
sizeof(struct fxp_softc),
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t fxp_devclass;
|
|
|
|
|
1999-09-22 06:08:11 +00:00
|
|
|
DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
|
1999-04-16 21:22:55 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
#endif /* __NetBSD__ */
|
|
|
|
|
|
|
|
/*************************************************************
|
|
|
|
* End of operating system-specific autoconfiguration glue
|
|
|
|
*************************************************************/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do generic parts of attach.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
fxp_attach_common(sc, enaddr)
|
|
|
|
struct fxp_softc *sc;
|
|
|
|
u_int8_t *enaddr;
|
|
|
|
{
|
|
|
|
u_int16_t data;
|
|
|
|
int i, nmedia, defmedia;
|
|
|
|
const int *media;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset to a stable state.
|
|
|
|
*/
|
|
|
|
CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
|
|
|
|
DELAY(10);
|
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
|
|
|
|
M_DEVBUF, M_NOWAIT);
|
|
|
|
if (sc->cbl_base == NULL)
|
1997-09-05 10:23:58 +00:00
|
|
|
goto fail;
|
1998-10-11 06:28:54 +00:00
|
|
|
bzero(sc->cbl_base, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, M_NOWAIT);
|
|
|
|
if (sc->fxp_stats == NULL)
|
1997-09-05 10:23:58 +00:00
|
|
|
goto fail;
|
1995-11-28 23:55:26 +00:00
|
|
|
bzero(sc->fxp_stats, sizeof(struct fxp_stats));
|
|
|
|
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
|
|
|
|
if (sc->mcsp == NULL)
|
|
|
|
goto fail;
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Pre-allocate our receive buffers.
|
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
for (i = 0; i < FXP_NRFABUFS; i++) {
|
|
|
|
if (fxp_add_rfabuf(sc, NULL) != 0) {
|
1997-09-05 10:23:58 +00:00
|
|
|
goto fail;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2000-03-28 04:41:42 +00:00
|
|
|
/*
|
|
|
|
* Find out how large of an SEEPROM we have.
|
|
|
|
*/
|
|
|
|
fxp_autosize_eeprom(sc);
|
|
|
|
|
1997-03-17 11:08:16 +00:00
|
|
|
/*
|
|
|
|
* Get info about the primary PHY
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_read_eeprom(sc, (u_int16_t *)&data, 6, 1);
|
1997-03-17 11:08:16 +00:00
|
|
|
sc->phy_primary_addr = data & 0xff;
|
|
|
|
sc->phy_primary_device = (data >> 8) & 0x3f;
|
|
|
|
sc->phy_10Mbps_only = data >> 15;
|
|
|
|
|
|
|
|
/*
|
1997-09-05 10:23:58 +00:00
|
|
|
* Read MAC address.
|
1997-03-17 11:08:16 +00:00
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_read_eeprom(sc, (u_int16_t *)enaddr, 0, 3);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
1997-09-05 10:23:58 +00:00
|
|
|
* Initialize the media structures.
|
1995-12-01 22:41:56 +00:00
|
|
|
*/
|
1996-02-06 18:51:28 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
media = fxp_media_default;
|
|
|
|
nmedia = sizeof(fxp_media_default) / sizeof(fxp_media_default[0]);
|
|
|
|
defmedia = FXP_MEDIA_DEFAULT_DEFMEDIA;
|
1996-09-20 04:11:53 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
for (i = 0; i < NFXPMEDIA; i++) {
|
|
|
|
if (sc->phy_primary_device == fxp_media[i].fsm_phy) {
|
|
|
|
media = fxp_media[i].fsm_media;
|
|
|
|
nmedia = fxp_media[i].fsm_nmedia;
|
|
|
|
defmedia = fxp_media[i].fsm_defmedia;
|
|
|
|
}
|
|
|
|
}
|
1996-09-20 04:11:53 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
ifmedia_init(&sc->sc_media, 0, fxp_mediachange, fxp_mediastatus);
|
|
|
|
for (i = 0; i < nmedia; i++) {
|
|
|
|
if (IFM_SUBTYPE(media[i]) == IFM_100_TX && sc->phy_10Mbps_only)
|
|
|
|
continue;
|
|
|
|
ifmedia_add(&sc->sc_media, media[i], 0, NULL);
|
|
|
|
}
|
|
|
|
ifmedia_set(&sc->sc_media, defmedia);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
return (0);
|
|
|
|
|
|
|
|
fail:
|
|
|
|
printf(FXP_FORMAT ": Failed to malloc memory\n", FXP_ARGS(sc));
|
|
|
|
if (sc->cbl_base)
|
1995-11-28 23:55:26 +00:00
|
|
|
free(sc->cbl_base, M_DEVBUF);
|
1997-09-05 10:23:58 +00:00
|
|
|
if (sc->fxp_stats)
|
1995-11-28 23:55:26 +00:00
|
|
|
free(sc->fxp_stats, M_DEVBUF);
|
1997-09-29 11:27:43 +00:00
|
|
|
if (sc->mcsp)
|
|
|
|
free(sc->mcsp, M_DEVBUF);
|
1995-11-28 23:55:26 +00:00
|
|
|
/* frees entire chain */
|
1997-09-05 10:23:58 +00:00
|
|
|
if (sc->rfa_headm)
|
1995-11-28 23:55:26 +00:00
|
|
|
m_freem(sc->rfa_headm);
|
1997-09-05 10:23:58 +00:00
|
|
|
|
|
|
|
return (ENOMEM);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
2000-03-28 04:41:42 +00:00
|
|
|
/*
|
|
|
|
* From NetBSD:
|
|
|
|
*
|
|
|
|
* Figure out EEPROM size.
|
|
|
|
*
|
|
|
|
* 559's can have either 64-word or 256-word EEPROMs, the 558
|
|
|
|
* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
|
|
|
|
* talks about the existance of 16 to 256 word EEPROMs.
|
|
|
|
*
|
|
|
|
* The only known sizes are 64 and 256, where the 256 version is used
|
|
|
|
* by CardBus cards to store CIS information.
|
|
|
|
*
|
|
|
|
* The address is shifted in msb-to-lsb, and after the last
|
|
|
|
* address-bit the EEPROM is supposed to output a `dummy zero' bit,
|
|
|
|
* after which follows the actual data. We try to detect this zero, by
|
|
|
|
* probing the data-out bit in the EEPROM control register just after
|
|
|
|
* having shifted in a bit. If the bit is zero, we assume we've
|
|
|
|
* shifted enough address bits. The data-out should be tri-state,
|
|
|
|
* before this, which should translate to a logical one.
|
|
|
|
*
|
|
|
|
* Other ways to do this would be to try to read a register with known
|
|
|
|
* contents with a varying number of address bits, but no such
|
|
|
|
* register seem to be available. The high bits of register 10 are 01
|
|
|
|
* on the 558 and 559, but apparently not on the 557.
|
|
|
|
*
|
|
|
|
* The Linux driver computes a checksum on the EEPROM data, but the
|
|
|
|
* value of this checksum is not very well documented.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
fxp_autosize_eeprom(sc)
|
|
|
|
struct fxp_softc *sc;
|
|
|
|
{
|
|
|
|
u_int16_t reg;
|
|
|
|
int x;
|
|
|
|
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
|
|
|
|
/*
|
|
|
|
* Shift in read opcode.
|
|
|
|
*/
|
|
|
|
for (x = 3; x > 0; x--) {
|
|
|
|
if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
|
|
|
|
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
|
|
|
|
} else {
|
|
|
|
reg = FXP_EEPROM_EECS;
|
|
|
|
}
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
|
|
|
|
reg | FXP_EEPROM_EESK);
|
|
|
|
DELAY(1);
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Shift in address.
|
|
|
|
* Wait for the dummy zero following a correct address shift.
|
|
|
|
*/
|
|
|
|
for (x = 1; x <= 8; x++) {
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
|
|
|
|
FXP_EEPROM_EECS | FXP_EEPROM_EESK);
|
|
|
|
DELAY(1);
|
|
|
|
if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) == 0)
|
|
|
|
break;
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
|
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
|
|
|
|
DELAY(1);
|
|
|
|
sc->eeprom_size = x;
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1997-03-17 11:08:16 +00:00
|
|
|
* Read from the serial EEPROM. Basically, you manually shift in
|
|
|
|
* the read opcode (one bit at a time) and then shift in the address,
|
|
|
|
* and then you shift out the data (all of this one bit at a time).
|
|
|
|
* The word size is 16 bits, so you have to provide the address for
|
|
|
|
* every 16 bits of data.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
|
|
|
static void
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_read_eeprom(sc, data, offset, words)
|
|
|
|
struct fxp_softc *sc;
|
1997-03-17 11:08:16 +00:00
|
|
|
u_short *data;
|
|
|
|
int offset;
|
|
|
|
int words;
|
|
|
|
{
|
1997-09-05 10:23:58 +00:00
|
|
|
u_int16_t reg;
|
1995-11-28 23:55:26 +00:00
|
|
|
int i, x;
|
|
|
|
|
1997-03-17 11:08:16 +00:00
|
|
|
for (i = 0; i < words; i++) {
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
|
|
|
* Shift in read opcode.
|
|
|
|
*/
|
|
|
|
for (x = 3; x > 0; x--) {
|
|
|
|
if (FXP_EEPROM_OPC_READ & (1 << (x - 1))) {
|
|
|
|
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
|
|
|
|
} else {
|
|
|
|
reg = FXP_EEPROM_EECS;
|
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
|
|
|
|
reg | FXP_EEPROM_EESK);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Shift in address.
|
|
|
|
*/
|
2000-03-28 04:41:42 +00:00
|
|
|
for (x = sc->eeprom_size; x > 0; x--) {
|
1997-03-17 11:08:16 +00:00
|
|
|
if ((i + offset) & (1 << (x - 1))) {
|
1995-11-28 23:55:26 +00:00
|
|
|
reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
|
|
|
|
} else {
|
|
|
|
reg = FXP_EEPROM_EECS;
|
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
|
|
|
|
reg | FXP_EEPROM_EESK);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
reg = FXP_EEPROM_EECS;
|
|
|
|
data[i] = 0;
|
|
|
|
/*
|
|
|
|
* Shift out data.
|
|
|
|
*/
|
|
|
|
for (x = 16; x > 0; x--) {
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
|
|
|
|
reg | FXP_EEPROM_EESK);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
1997-09-05 10:23:58 +00:00
|
|
|
if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
|
|
|
|
FXP_EEPROM_EEDO)
|
1995-11-28 23:55:26 +00:00
|
|
|
data[i] |= (1 << (x - 1));
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start packet transmission on the interface.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
fxp_start(ifp)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
1996-02-06 18:51:28 +00:00
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
1995-11-28 23:55:26 +00:00
|
|
|
struct fxp_cb_tx *txp;
|
|
|
|
|
|
|
|
/*
|
1997-10-23 01:45:15 +00:00
|
|
|
* See if we need to suspend xmit until the multicast filter
|
|
|
|
* has been reprogrammed (which can only be done at the head
|
|
|
|
* of the command chain).
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-10-23 01:45:15 +00:00
|
|
|
if (sc->need_mcsetup)
|
1995-11-28 23:55:26 +00:00
|
|
|
return;
|
1996-09-22 11:48:54 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
txp = NULL;
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
1997-10-23 01:45:15 +00:00
|
|
|
* We're finished if there is nothing more to add to the list or if
|
|
|
|
* we're all filled up with buffers to transmit.
|
1998-08-04 08:53:12 +00:00
|
|
|
* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
|
|
|
|
* a NOP command when needed.
|
1995-12-01 22:41:56 +00:00
|
|
|
*/
|
1998-08-04 08:53:12 +00:00
|
|
|
while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
|
1997-10-23 01:45:15 +00:00
|
|
|
struct mbuf *m, *mb_head;
|
|
|
|
int segment;
|
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1997-10-23 01:45:15 +00:00
|
|
|
* Grab a packet to transmit.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-10-23 01:45:15 +00:00
|
|
|
IF_DEQUEUE(&ifp->if_snd, mb_head);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
|
|
|
* Get pointer to next available tx desc.
|
|
|
|
*/
|
|
|
|
txp = sc->cbl_last->next;
|
1995-12-05 11:49:55 +00:00
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1997-10-23 01:45:15 +00:00
|
|
|
* Go through each of the mbufs in the chain and initialize
|
|
|
|
* the transmit buffer descriptors with the physical address
|
|
|
|
* and size of the mbuf.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-10-23 01:45:15 +00:00
|
|
|
tbdinit:
|
|
|
|
for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
|
|
|
|
if (m->m_len != 0) {
|
|
|
|
if (segment == FXP_NTXSEG)
|
|
|
|
break;
|
|
|
|
txp->tbd[segment].tb_addr =
|
|
|
|
vtophys(mtod(m, vm_offset_t));
|
|
|
|
txp->tbd[segment].tb_size = m->m_len;
|
|
|
|
segment++;
|
|
|
|
}
|
1995-12-05 11:49:55 +00:00
|
|
|
}
|
1997-10-23 01:45:15 +00:00
|
|
|
if (m != NULL) {
|
|
|
|
struct mbuf *mn;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We ran out of segments. We have to recopy this mbuf
|
|
|
|
* chain first. Bail out if we can't get the new buffers.
|
|
|
|
*/
|
|
|
|
MGETHDR(mn, M_DONTWAIT, MT_DATA);
|
|
|
|
if (mn == NULL) {
|
1995-12-05 11:49:55 +00:00
|
|
|
m_freem(mb_head);
|
1997-10-23 01:45:15 +00:00
|
|
|
break;
|
1995-12-05 11:49:55 +00:00
|
|
|
}
|
1997-10-23 01:45:15 +00:00
|
|
|
if (mb_head->m_pkthdr.len > MHLEN) {
|
|
|
|
MCLGET(mn, M_DONTWAIT);
|
|
|
|
if ((mn->m_flags & M_EXT) == 0) {
|
|
|
|
m_freem(mn);
|
|
|
|
m_freem(mb_head);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
|
|
|
|
mtod(mn, caddr_t));
|
|
|
|
mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
|
|
|
|
m_freem(mb_head);
|
|
|
|
mb_head = mn;
|
|
|
|
goto tbdinit;
|
1995-12-05 11:49:55 +00:00
|
|
|
}
|
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
txp->tbd_number = segment;
|
|
|
|
txp->mb_head = mb_head;
|
|
|
|
txp->cb_status = 0;
|
1998-08-04 08:53:12 +00:00
|
|
|
if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
|
|
|
|
txp->cb_command =
|
|
|
|
FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S;
|
|
|
|
} else {
|
|
|
|
txp->cb_command =
|
|
|
|
FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
|
|
|
|
/*
|
|
|
|
* Set a 5 second timer just in case we don't hear from the
|
|
|
|
* card again.
|
|
|
|
*/
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
}
|
1997-10-23 01:45:15 +00:00
|
|
|
txp->tx_threshold = tx_threshold;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
|
|
|
* Advance the end of list forward.
|
|
|
|
*/
|
|
|
|
sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
|
|
|
|
sc->cbl_last = txp;
|
1996-09-22 11:48:54 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
|
|
|
* Advance the beginning of the list forward if there are
|
|
|
|
* no other packets queued (when nothing is queued, cbl_first
|
|
|
|
* sits on the last TxCB that was sent out).
|
|
|
|
*/
|
|
|
|
if (sc->tx_queued == 0)
|
|
|
|
sc->cbl_first = txp;
|
1996-01-03 05:22:32 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
sc->tx_queued++;
|
1996-09-29 10:20:45 +00:00
|
|
|
|
1997-10-23 01:45:15 +00:00
|
|
|
/*
|
|
|
|
* Pass packet to bpf if there is a listener.
|
|
|
|
*/
|
|
|
|
if (ifp->if_bpf)
|
|
|
|
bpf_mtap(FXP_BPFTAP_ARG(ifp), mb_head);
|
|
|
|
}
|
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1997-10-23 01:45:15 +00:00
|
|
|
* We're finished. If we added to the list, issue a RESUME to get DMA
|
|
|
|
* going again if suspended.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-10-23 01:45:15 +00:00
|
|
|
if (txp != NULL) {
|
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
1996-11-18 02:45:46 +00:00
|
|
|
* Process interface interrupts.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
static FXP_INTR_TYPE
|
1995-11-28 23:55:26 +00:00
|
|
|
fxp_intr(arg)
|
|
|
|
void *arg;
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = arg;
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifnet *ifp = &sc->sc_if;
|
1996-09-22 11:48:54 +00:00
|
|
|
u_int8_t statack;
|
1997-09-05 10:23:58 +00:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
int claimed = 0;
|
|
|
|
#endif
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
|
|
|
|
#if defined(__NetBSD__)
|
|
|
|
claimed = 1;
|
|
|
|
#endif
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
|
|
|
* First ACK all the interrupts in this pass.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1998-08-04 08:53:12 +00:00
|
|
|
/*
|
|
|
|
* Free any finished transmit mbuf chains.
|
|
|
|
*/
|
|
|
|
if (statack & FXP_SCB_STATACK_CXTNO) {
|
|
|
|
struct fxp_cb_tx *txp;
|
|
|
|
|
|
|
|
for (txp = sc->cbl_first; sc->tx_queued &&
|
|
|
|
(txp->cb_status & FXP_CB_STATUS_C) != 0;
|
|
|
|
txp = txp->next) {
|
|
|
|
if (txp->mb_head != NULL) {
|
|
|
|
m_freem(txp->mb_head);
|
|
|
|
txp->mb_head = NULL;
|
|
|
|
}
|
|
|
|
sc->tx_queued--;
|
|
|
|
}
|
|
|
|
sc->cbl_first = txp;
|
|
|
|
ifp->if_timer = 0;
|
|
|
|
if (sc->tx_queued == 0) {
|
|
|
|
if (sc->need_mcsetup)
|
|
|
|
fxp_mc_setup(sc);
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Try to start more packets transmitting.
|
|
|
|
*/
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
|
|
fxp_start(ifp);
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
|
|
|
* Process receiver interrupts. If a no-resource (RNR)
|
|
|
|
* condition exists, get whatever packets we can and
|
|
|
|
* re-start the receiver.
|
|
|
|
*/
|
|
|
|
if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
|
|
|
|
struct mbuf *m;
|
|
|
|
struct fxp_rfa *rfa;
|
|
|
|
rcvloop:
|
|
|
|
m = sc->rfa_headm;
|
1997-09-05 10:23:58 +00:00
|
|
|
rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
|
|
|
|
RFA_ALIGNMENT_FUDGE);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
if (rfa->rfa_status & FXP_RFA_STATUS_C) {
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Remove first packet from the chain.
|
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
sc->rfa_headm = m->m_next;
|
|
|
|
m->m_next = NULL;
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
1997-09-05 10:23:58 +00:00
|
|
|
* Add a new buffer to the receive chain.
|
|
|
|
* If this fails, the old buffer is recycled
|
|
|
|
* instead.
|
1995-12-01 22:41:56 +00:00
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
if (fxp_add_rfabuf(sc, m) == 0) {
|
|
|
|
struct ether_header *eh;
|
1997-09-05 10:23:58 +00:00
|
|
|
u_int16_t total_len;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
total_len = rfa->actual_size &
|
|
|
|
(MCLBYTES - 1);
|
|
|
|
if (total_len <
|
|
|
|
sizeof(struct ether_header)) {
|
1997-04-23 01:44:30 +00:00
|
|
|
m_freem(m);
|
|
|
|
goto rcvloop;
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
m->m_pkthdr.rcvif = ifp;
|
1997-09-05 10:23:58 +00:00
|
|
|
m->m_pkthdr.len = m->m_len =
|
1999-03-17 16:44:53 +00:00
|
|
|
total_len ;
|
1995-11-28 23:55:26 +00:00
|
|
|
eh = mtod(m, struct ether_header *);
|
1999-03-17 16:44:53 +00:00
|
|
|
if (ifp->if_bpf)
|
1997-09-05 10:23:58 +00:00
|
|
|
bpf_tap(FXP_BPFTAP_ARG(ifp),
|
|
|
|
mtod(m, caddr_t),
|
|
|
|
total_len);
|
1999-03-17 16:44:53 +00:00
|
|
|
#ifdef BRIDGE
|
|
|
|
if (do_bridge) {
|
|
|
|
struct ifnet *bdg_ifp ;
|
|
|
|
bdg_ifp = bridge_in(m);
|
|
|
|
if (bdg_ifp == BDG_DROP)
|
|
|
|
goto dropit ;
|
|
|
|
if (bdg_ifp != BDG_LOCAL)
|
|
|
|
bdg_forward(&m, bdg_ifp);
|
|
|
|
if (bdg_ifp != BDG_LOCAL &&
|
|
|
|
bdg_ifp != BDG_BCAST &&
|
|
|
|
bdg_ifp != BDG_MCAST)
|
|
|
|
goto dropit ;
|
|
|
|
goto getit ;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* Only pass this packet up
|
|
|
|
* if it is for us.
|
|
|
|
*/
|
|
|
|
if ((ifp->if_flags &
|
|
|
|
IFF_PROMISC) &&
|
|
|
|
(rfa->rfa_status &
|
|
|
|
FXP_RFA_STATUS_IAMATCH) &&
|
|
|
|
(eh->ether_dhost[0] & 1)
|
|
|
|
== 0) {
|
1999-05-09 10:45:54 +00:00
|
|
|
#ifdef BRIDGE
|
1999-03-17 16:44:53 +00:00
|
|
|
dropit:
|
1999-05-09 10:45:54 +00:00
|
|
|
#endif
|
1999-03-17 16:44:53 +00:00
|
|
|
if (m)
|
|
|
|
m_freem(m);
|
|
|
|
goto rcvloop;
|
|
|
|
}
|
1999-05-09 10:45:54 +00:00
|
|
|
#ifdef BRIDGE
|
1999-03-17 16:44:53 +00:00
|
|
|
getit:
|
1999-05-09 10:45:54 +00:00
|
|
|
#endif
|
1997-09-05 10:23:58 +00:00
|
|
|
m->m_data +=
|
|
|
|
sizeof(struct ether_header);
|
1999-03-17 16:44:53 +00:00
|
|
|
m->m_len -=
|
|
|
|
sizeof(struct ether_header);
|
|
|
|
m->m_pkthdr.len = m->m_len ;
|
1995-11-28 23:55:26 +00:00
|
|
|
ether_input(ifp, eh, m);
|
|
|
|
}
|
|
|
|
goto rcvloop;
|
|
|
|
}
|
|
|
|
if (statack & FXP_SCB_STATACK_RNR) {
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
|
|
|
|
vtophys(sc->rfa_headm->m_ext.ext_buf) +
|
|
|
|
RFA_ALIGNMENT_FUDGE);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
|
|
|
|
FXP_SCB_COMMAND_RU_START);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
return (claimed);
|
|
|
|
#endif
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* Update packet in/out/collision statistics. The i82557 doesn't
|
|
|
|
* allow you to access these counters without doing a fairly
|
|
|
|
* expensive DMA to get _all_ of the statistics it maintains, so
|
|
|
|
* we do this operation here only once per second. The statistics
|
|
|
|
* counters in the kernel are updated from the previous dump-stats
|
|
|
|
* DMA and then a new dump-stats DMA is started. The on-chip
|
|
|
|
* counters are zeroed when the DMA completes. If we can't start
|
|
|
|
* the DMA immediately, we don't wait - we just prepare to read
|
|
|
|
* them again next time.
|
|
|
|
*/
|
1998-02-09 06:11:36 +00:00
|
|
|
static void
|
1995-11-28 23:55:26 +00:00
|
|
|
fxp_stats_update(arg)
|
|
|
|
void *arg;
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = arg;
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifnet *ifp = &sc->sc_if;
|
1995-11-28 23:55:26 +00:00
|
|
|
struct fxp_stats *sp = sc->fxp_stats;
|
1998-10-22 02:00:49 +00:00
|
|
|
struct fxp_cb_tx *txp;
|
1997-09-29 11:27:43 +00:00
|
|
|
int s;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
ifp->if_opackets += sp->tx_good;
|
|
|
|
ifp->if_collisions += sp->tx_total_collisions;
|
1997-09-29 11:27:43 +00:00
|
|
|
if (sp->rx_good) {
|
|
|
|
ifp->if_ipackets += sp->rx_good;
|
|
|
|
sc->rx_idle_secs = 0;
|
|
|
|
} else {
|
1998-10-22 02:00:49 +00:00
|
|
|
/*
|
|
|
|
* Receiver's been idle for another second.
|
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->rx_idle_secs++;
|
|
|
|
}
|
1996-01-03 05:22:32 +00:00
|
|
|
ifp->if_ierrors +=
|
|
|
|
sp->rx_crc_errors +
|
|
|
|
sp->rx_alignment_errors +
|
|
|
|
sp->rx_rnr_errors +
|
1997-02-04 07:39:28 +00:00
|
|
|
sp->rx_overrun_errors;
|
1996-09-19 09:15:20 +00:00
|
|
|
/*
|
|
|
|
* If any transmit underruns occured, bump up the transmit
|
|
|
|
* threshold by another 512 bytes (64 * 8).
|
|
|
|
*/
|
|
|
|
if (sp->tx_underruns) {
|
|
|
|
ifp->if_oerrors += sp->tx_underruns;
|
|
|
|
if (tx_threshold < 192)
|
|
|
|
tx_threshold += 64;
|
|
|
|
}
|
1997-09-29 11:27:43 +00:00
|
|
|
s = splimp();
|
1998-10-22 02:00:49 +00:00
|
|
|
/*
|
|
|
|
* Release any xmit buffers that have completed DMA. This isn't
|
|
|
|
* strictly necessary to do here, but it's advantagous for mbufs
|
|
|
|
* with external storage to be released in a timely manner rather
|
|
|
|
* than being defered for a potentially long time. This limits
|
|
|
|
* the delay to a maximum of one second.
|
|
|
|
*/
|
|
|
|
for (txp = sc->cbl_first; sc->tx_queued &&
|
|
|
|
(txp->cb_status & FXP_CB_STATUS_C) != 0;
|
|
|
|
txp = txp->next) {
|
|
|
|
if (txp->mb_head != NULL) {
|
|
|
|
m_freem(txp->mb_head);
|
|
|
|
txp->mb_head = NULL;
|
|
|
|
}
|
|
|
|
sc->tx_queued--;
|
|
|
|
}
|
|
|
|
sc->cbl_first = txp;
|
1997-09-29 11:27:43 +00:00
|
|
|
/*
|
|
|
|
* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
|
|
|
|
* then assume the receiver has locked up and attempt to clear
|
|
|
|
* the condition by reprogramming the multicast filter. This is
|
|
|
|
* a work-around for a bug in the 82557 where the receiver locks
|
|
|
|
* up if it gets certain types of garbage in the syncronization
|
|
|
|
* bits prior to the packet header. This bug is supposed to only
|
|
|
|
* occur in 10Mbps mode, but has been seen to occur in 100Mbps
|
|
|
|
* mode as well (perhaps due to a 10/100 speed transition).
|
|
|
|
*/
|
|
|
|
if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
|
|
|
|
sc->rx_idle_secs = 0;
|
|
|
|
fxp_mc_setup(sc);
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1996-01-03 05:22:32 +00:00
|
|
|
* If there is no pending command, start another stats
|
|
|
|
* dump. Otherwise punt for now.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
1997-09-29 11:27:43 +00:00
|
|
|
* Start another stats dump.
|
1995-12-01 22:41:56 +00:00
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND,
|
|
|
|
FXP_SCB_COMMAND_CU_DUMPRESET);
|
1995-12-01 22:41:56 +00:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* A previous command is still waiting to be accepted.
|
|
|
|
* Just zero our copy of the stats and wait for the
|
1996-01-03 05:22:32 +00:00
|
|
|
* next timer event to update them.
|
1995-12-01 22:41:56 +00:00
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
sp->tx_good = 0;
|
1996-09-19 09:15:20 +00:00
|
|
|
sp->tx_underruns = 0;
|
1995-11-28 23:55:26 +00:00
|
|
|
sp->tx_total_collisions = 0;
|
1996-01-03 05:22:32 +00:00
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
sp->rx_good = 0;
|
1996-01-03 05:22:32 +00:00
|
|
|
sp->rx_crc_errors = 0;
|
|
|
|
sp->rx_alignment_errors = 0;
|
|
|
|
sp->rx_rnr_errors = 0;
|
|
|
|
sp->rx_overrun_errors = 0;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
1997-09-29 11:27:43 +00:00
|
|
|
splx(s);
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
|
|
|
* Schedule another timeout one second from now.
|
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->stat_ch = timeout(fxp_stats_update, sc, hz);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop the interface. Cancels the statistics updater and resets
|
|
|
|
* the interface.
|
|
|
|
*/
|
|
|
|
static void
|
1995-12-05 02:01:59 +00:00
|
|
|
fxp_stop(sc)
|
|
|
|
struct fxp_softc *sc;
|
1995-11-28 23:55:26 +00:00
|
|
|
{
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifnet *ifp = &sc->sc_if;
|
1996-01-03 05:22:32 +00:00
|
|
|
struct fxp_cb_tx *txp;
|
|
|
|
int i;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Cancel stats updater.
|
|
|
|
*/
|
1997-09-21 22:02:25 +00:00
|
|
|
untimeout(fxp_stats_update, sc, sc->stat_ch);
|
1996-01-03 05:22:32 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Issue software reset
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
|
1995-11-28 23:55:26 +00:00
|
|
|
DELAY(10);
|
|
|
|
|
1996-01-03 05:22:32 +00:00
|
|
|
/*
|
|
|
|
* Release any xmit buffers.
|
|
|
|
*/
|
1998-10-10 19:26:40 +00:00
|
|
|
txp = sc->cbl_base;
|
|
|
|
if (txp != NULL) {
|
|
|
|
for (i = 0; i < FXP_NTXCB; i++) {
|
|
|
|
if (txp[i].mb_head != NULL) {
|
|
|
|
m_freem(txp[i].mb_head);
|
|
|
|
txp[i].mb_head = NULL;
|
|
|
|
}
|
|
|
|
}
|
1996-01-03 05:22:32 +00:00
|
|
|
}
|
|
|
|
sc->tx_queued = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free all the receive buffers then reallocate/reinitialize
|
|
|
|
*/
|
|
|
|
if (sc->rfa_headm != NULL)
|
|
|
|
m_freem(sc->rfa_headm);
|
|
|
|
sc->rfa_headm = NULL;
|
|
|
|
sc->rfa_tailm = NULL;
|
|
|
|
for (i = 0; i < FXP_NRFABUFS; i++) {
|
|
|
|
if (fxp_add_rfabuf(sc, NULL) != 0) {
|
|
|
|
/*
|
|
|
|
* This "can't happen" - we're at splimp()
|
|
|
|
* and we just freed all the buffers we need
|
|
|
|
* above.
|
|
|
|
*/
|
|
|
|
panic("fxp_stop: no buffers!");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
|
|
|
ifp->if_timer = 0;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Watchdog/transmission transmit timeout handler. Called when a
|
|
|
|
* transmission is started on the interface, but no interrupt is
|
|
|
|
* received before the timeout. This usually indicates that the
|
|
|
|
* card has wedged for some reason.
|
|
|
|
*/
|
|
|
|
static void
|
1995-12-05 02:01:59 +00:00
|
|
|
fxp_watchdog(ifp)
|
|
|
|
struct ifnet *ifp;
|
1995-11-28 23:55:26 +00:00
|
|
|
{
|
1997-09-05 10:23:58 +00:00
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
|
|
|
|
1997-09-29 11:27:43 +00:00
|
|
|
printf(FXP_FORMAT ": device timeout\n", FXP_ARGS(sc));
|
1995-12-05 02:01:59 +00:00
|
|
|
ifp->if_oerrors++;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_init(sc);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
1996-12-10 07:29:50 +00:00
|
|
|
fxp_init(xsc)
|
|
|
|
void *xsc;
|
1995-11-28 23:55:26 +00:00
|
|
|
{
|
1996-12-10 07:29:50 +00:00
|
|
|
struct fxp_softc *sc = xsc;
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifnet *ifp = &sc->sc_if;
|
1995-11-28 23:55:26 +00:00
|
|
|
struct fxp_cb_config *cbp;
|
|
|
|
struct fxp_cb_ias *cb_ias;
|
|
|
|
struct fxp_cb_tx *txp;
|
1997-09-29 11:27:43 +00:00
|
|
|
int i, s, prm;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
/*
|
1996-01-03 05:22:32 +00:00
|
|
|
* Cancel any pending I/O
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1996-01-03 05:22:32 +00:00
|
|
|
fxp_stop(sc);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize base of CBL and RFA memory. Loading with zero
|
|
|
|
* sets it up for regular linear addressing.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_BASE);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_BASE);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize base of dump-stats buffer.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_DUMP_ADR);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We temporarily use memory that contains the TxCB list to
|
|
|
|
* construct the config CB. The TxCB list memory is rebuilt
|
|
|
|
* later.
|
|
|
|
*/
|
|
|
|
cbp = (struct fxp_cb_config *) sc->cbl_base;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This bcopy is kind of disgusting, but there are a bunch of must be
|
|
|
|
* zero and must be one bits in this structure and this is the easiest
|
|
|
|
* way to initialize them all to proper values.
|
|
|
|
*/
|
1999-01-28 17:32:05 +00:00
|
|
|
bcopy(fxp_cb_config_template, (volatile void *)&cbp->cb_status,
|
1997-09-29 11:27:43 +00:00
|
|
|
sizeof(fxp_cb_config_template));
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
cbp->cb_status = 0;
|
|
|
|
cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
|
|
|
|
cbp->link_addr = -1; /* (no) next command */
|
|
|
|
cbp->byte_count = 22; /* (22) bytes to config */
|
1997-02-04 11:44:15 +00:00
|
|
|
cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
|
|
|
|
cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
|
1997-02-04 11:44:15 +00:00
|
|
|
cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
|
|
|
|
cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
|
|
|
|
cbp->dma_bce = 0; /* (disable) dma max counters */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->late_scb = 0; /* (don't) defer SCB update */
|
|
|
|
cbp->tno_int = 0; /* (disable) tx not okay interrupt */
|
1998-08-04 08:53:12 +00:00
|
|
|
cbp->ci_int = 1; /* interrupt on CU idle */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->save_bf = prm; /* save bad frames */
|
|
|
|
cbp->disc_short_rx = !prm; /* discard short packets */
|
|
|
|
cbp->underrun_retry = 1; /* retry mode (1) on DMA underrun */
|
1997-03-17 11:08:16 +00:00
|
|
|
cbp->mediatype = !sc->phy_10Mbps_only; /* interface mode */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->nsai = 1; /* (don't) disable source addr insert */
|
|
|
|
cbp->preamble_length = 2; /* (7 byte) preamble */
|
|
|
|
cbp->loopback = 0; /* (don't) loopback */
|
|
|
|
cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
|
|
|
|
cbp->linear_pri_mode = 0; /* (wait after xmit only) */
|
|
|
|
cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
|
|
|
|
cbp->promiscuous = prm; /* promiscuous mode */
|
|
|
|
cbp->bcast_disable = 0; /* (don't) disable broadcasts */
|
1997-02-04 11:44:15 +00:00
|
|
|
cbp->crscdt = 0; /* (CRS only) */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->stripping = !prm; /* truncate rx packet to byte count */
|
|
|
|
cbp->padding = 1; /* (do) pad short tx packets */
|
|
|
|
cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
|
|
|
|
cbp->force_fdx = 0; /* (don't) force full duplex */
|
1996-01-03 05:22:32 +00:00
|
|
|
cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
|
1995-11-28 23:55:26 +00:00
|
|
|
cbp->multi_ia = 0; /* (don't) accept multiple IAs */
|
1997-09-29 11:27:43 +00:00
|
|
|
cbp->mc_all = sc->all_mcasts;/* accept all multicasts */
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Start the config command/DMA.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
1997-09-29 11:27:43 +00:00
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
|
1995-11-28 23:55:26 +00:00
|
|
|
/* ...and wait for it to complete. */
|
|
|
|
while (!(cbp->cb_status & FXP_CB_STATUS_C));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now initialize the station address. Temporarily use the TxCB
|
|
|
|
* memory area like we did above for the config CB.
|
|
|
|
*/
|
|
|
|
cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
|
|
|
|
cb_ias->cb_status = 0;
|
|
|
|
cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
|
|
|
|
cb_ias->link_addr = -1;
|
1997-09-05 10:23:58 +00:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
bcopy(LLADDR(ifp->if_sadl), (void *)cb_ias->macaddr, 6);
|
|
|
|
#else
|
1999-01-28 00:57:57 +00:00
|
|
|
bcopy(sc->arpcom.ac_enaddr, (volatile void *)cb_ias->macaddr,
|
1995-11-28 23:55:26 +00:00
|
|
|
sizeof(sc->arpcom.ac_enaddr));
|
1997-09-05 10:23:58 +00:00
|
|
|
#endif /* __NetBSD__ */
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Start the IAS (Individual Address Setup) command/DMA.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
|
1995-11-28 23:55:26 +00:00
|
|
|
/* ...and wait for it to complete. */
|
|
|
|
while (!(cb_ias->cb_status & FXP_CB_STATUS_C));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize transmit control block (TxCB) list.
|
|
|
|
*/
|
|
|
|
|
|
|
|
txp = sc->cbl_base;
|
|
|
|
bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
|
|
|
|
for (i = 0; i < FXP_NTXCB; i++) {
|
|
|
|
txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
|
|
|
|
txp[i].cb_command = FXP_CB_COMMAND_NOP;
|
1997-09-29 11:27:43 +00:00
|
|
|
txp[i].link_addr = vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
|
1995-11-28 23:55:26 +00:00
|
|
|
txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
|
|
|
|
txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
|
|
|
|
}
|
|
|
|
/*
|
1997-09-29 11:27:43 +00:00
|
|
|
* Set the suspend flag on the first TxCB and start the control
|
1995-11-28 23:55:26 +00:00
|
|
|
* unit. It will execute the NOP and then suspend.
|
|
|
|
*/
|
|
|
|
txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
|
|
|
|
sc->cbl_first = sc->cbl_last = txp;
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->tx_queued = 1;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize receiver buffer area - RFA.
|
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
|
|
|
|
vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_RU_START);
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-03-17 11:08:16 +00:00
|
|
|
/*
|
1997-09-05 10:23:58 +00:00
|
|
|
* Set current media.
|
1997-03-17 11:08:16 +00:00
|
|
|
*/
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
|
|
|
|
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
splx(s);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start stats updater.
|
|
|
|
*/
|
1997-09-21 22:02:25 +00:00
|
|
|
sc->stat_ch = timeout(fxp_stats_update, sc, hz);
|
1997-09-05 10:23:58 +00:00
|
|
|
}
|
|
|
|
|
1998-02-09 06:11:36 +00:00
|
|
|
static void
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_set_media(sc, media)
|
|
|
|
struct fxp_softc *sc;
|
|
|
|
int media;
|
|
|
|
{
|
|
|
|
|
1997-06-13 22:34:52 +00:00
|
|
|
switch (sc->phy_primary_device) {
|
|
|
|
case FXP_PHY_DP83840:
|
|
|
|
case FXP_PHY_DP83840A:
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_mdi_write(sc, sc->phy_primary_addr, FXP_DP83840_PCR,
|
|
|
|
fxp_mdi_read(sc, sc->phy_primary_addr, FXP_DP83840_PCR) |
|
1997-03-17 11:08:16 +00:00
|
|
|
FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
|
|
|
|
FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
|
|
|
|
FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
|
1997-06-13 22:34:52 +00:00
|
|
|
/* fall through */
|
1998-03-03 14:19:09 +00:00
|
|
|
case FXP_PHY_82553A:
|
|
|
|
case FXP_PHY_82553C: /* untested */
|
1997-06-13 22:34:52 +00:00
|
|
|
case FXP_PHY_82555:
|
1998-03-03 14:19:09 +00:00
|
|
|
case FXP_PHY_82555B:
|
1997-09-05 10:23:58 +00:00
|
|
|
if (IFM_SUBTYPE(media) != IFM_AUTO) {
|
1997-03-21 08:00:13 +00:00
|
|
|
int flags;
|
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
flags = (IFM_SUBTYPE(media) == IFM_100_TX) ?
|
|
|
|
FXP_PHY_BMCR_SPEED_100M : 0;
|
|
|
|
flags |= (media & IFM_FDX) ?
|
|
|
|
FXP_PHY_BMCR_FULLDUPLEX : 0;
|
|
|
|
fxp_mdi_write(sc, sc->phy_primary_addr,
|
|
|
|
FXP_PHY_BMCR,
|
|
|
|
(fxp_mdi_read(sc, sc->phy_primary_addr,
|
|
|
|
FXP_PHY_BMCR) &
|
1997-06-13 22:34:52 +00:00
|
|
|
~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
|
|
|
|
FXP_PHY_BMCR_FULLDUPLEX)) | flags);
|
1997-03-21 08:00:13 +00:00
|
|
|
} else {
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_mdi_write(sc, sc->phy_primary_addr,
|
|
|
|
FXP_PHY_BMCR,
|
|
|
|
(fxp_mdi_read(sc, sc->phy_primary_addr,
|
|
|
|
FXP_PHY_BMCR) | FXP_PHY_BMCR_AUTOEN));
|
1997-03-21 08:00:13 +00:00
|
|
|
}
|
1997-06-13 22:34:52 +00:00
|
|
|
break;
|
1997-07-25 23:41:12 +00:00
|
|
|
/*
|
|
|
|
* The Seeq 80c24 doesn't have a PHY programming interface, so do
|
|
|
|
* nothing.
|
|
|
|
*/
|
|
|
|
case FXP_PHY_80C24:
|
|
|
|
break;
|
1997-06-13 22:34:52 +00:00
|
|
|
default:
|
1997-09-05 10:23:58 +00:00
|
|
|
printf(FXP_FORMAT
|
|
|
|
": warning: unsupported PHY, type = %d, addr = %d\n",
|
|
|
|
FXP_ARGS(sc), sc->phy_primary_device,
|
|
|
|
sc->phy_primary_addr);
|
1997-03-17 11:08:16 +00:00
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
}
|
1997-03-17 11:08:16 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
/*
|
|
|
|
* Change media according to request.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
fxp_mediachange(ifp)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
|
|
|
struct ifmedia *ifm = &sc->sc_media;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
fxp_set_media(sc, ifm->ifm_media);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Notify the world which media we're using.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
fxp_mediastatus(ifp, ifmr)
|
|
|
|
struct ifnet *ifp;
|
|
|
|
struct ifmediareq *ifmr;
|
|
|
|
{
|
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
1999-02-12 17:56:23 +00:00
|
|
|
int flags, stsflags;
|
1997-09-05 10:23:58 +00:00
|
|
|
|
|
|
|
switch (sc->phy_primary_device) {
|
|
|
|
case FXP_PHY_82555:
|
1998-08-02 00:33:38 +00:00
|
|
|
case FXP_PHY_82555B:
|
1999-02-12 17:56:23 +00:00
|
|
|
case FXP_PHY_DP83840:
|
|
|
|
case FXP_PHY_DP83840A:
|
|
|
|
ifmr->ifm_status = IFM_AVALID; /* IFM_ACTIVE will be valid */
|
1997-09-05 10:23:58 +00:00
|
|
|
ifmr->ifm_active = IFM_ETHER;
|
1999-02-12 17:56:23 +00:00
|
|
|
/*
|
|
|
|
* the following is not an error.
|
|
|
|
* You need to read this register twice to get current
|
|
|
|
* status. This is correct documented behaviour, the
|
|
|
|
* first read gets latched values.
|
|
|
|
*/
|
|
|
|
stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
|
|
|
|
stsflags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_STS);
|
|
|
|
if (stsflags & FXP_PHY_STS_LINK_STS)
|
|
|
|
ifmr->ifm_status |= IFM_ACTIVE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we are in auto mode, then try report the result.
|
|
|
|
*/
|
|
|
|
flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
|
1999-02-11 21:47:10 +00:00
|
|
|
if (flags & FXP_PHY_BMCR_AUTOEN) {
|
|
|
|
ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
|
1999-02-12 17:56:23 +00:00
|
|
|
if (stsflags & FXP_PHY_STS_AUTO_DONE) {
|
|
|
|
/*
|
|
|
|
* Intel and National parts report
|
|
|
|
* differently on what they found.
|
|
|
|
*/
|
|
|
|
if ((sc->phy_primary_device == FXP_PHY_82555)
|
|
|
|
|| (sc->phy_primary_device == FXP_PHY_82555B)) {
|
|
|
|
flags = fxp_mdi_read(sc,
|
|
|
|
sc->phy_primary_addr,
|
|
|
|
FXP_PHY_USC);
|
|
|
|
|
|
|
|
if (flags & FXP_PHY_USC_SPEED)
|
|
|
|
ifmr->ifm_active |= IFM_100_TX;
|
|
|
|
else
|
|
|
|
ifmr->ifm_active |= IFM_10_T;
|
|
|
|
|
|
|
|
if (flags & FXP_PHY_USC_DUPLEX)
|
|
|
|
ifmr->ifm_active |= IFM_FDX;
|
|
|
|
} else { /* it's National. only know speed */
|
|
|
|
flags = fxp_mdi_read(sc,
|
|
|
|
sc->phy_primary_addr,
|
|
|
|
FXP_DP83840_PAR);
|
1999-02-11 21:47:10 +00:00
|
|
|
|
1999-02-12 17:56:23 +00:00
|
|
|
if (flags & FXP_DP83840_PAR_SPEED_10)
|
|
|
|
ifmr->ifm_active |= IFM_10_T;
|
|
|
|
else
|
|
|
|
ifmr->ifm_active |= IFM_100_TX;
|
|
|
|
}
|
1999-02-11 21:47:10 +00:00
|
|
|
}
|
1999-02-12 17:56:23 +00:00
|
|
|
} else { /* in manual mode.. just report what we were set to */
|
1997-09-05 10:23:58 +00:00
|
|
|
if (flags & FXP_PHY_BMCR_SPEED_100M)
|
|
|
|
ifmr->ifm_active |= IFM_100_TX;
|
|
|
|
else
|
|
|
|
ifmr->ifm_active |= IFM_10_T;
|
|
|
|
|
|
|
|
if (flags & FXP_PHY_BMCR_FULLDUPLEX)
|
|
|
|
ifmr->ifm_active |= IFM_FDX;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FXP_PHY_80C24:
|
|
|
|
default:
|
|
|
|
ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; /* XXX IFM_AUTO ? */
|
|
|
|
}
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Add a buffer to the end of the RFA buffer list.
|
|
|
|
* Return 0 if successful, 1 for failure. A failure results in
|
|
|
|
* adding the 'oldm' (if non-NULL) on to the end of the list -
|
1998-04-17 22:37:19 +00:00
|
|
|
* tossing out its old contents and recycling it.
|
1995-11-28 23:55:26 +00:00
|
|
|
* The RFA struct is stuck at the beginning of mbuf cluster and the
|
|
|
|
* data pointer is fixed up to point just past it.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
fxp_add_rfabuf(sc, oldm)
|
|
|
|
struct fxp_softc *sc;
|
|
|
|
struct mbuf *oldm;
|
|
|
|
{
|
1997-09-05 10:23:58 +00:00
|
|
|
u_int32_t v;
|
1995-11-28 23:55:26 +00:00
|
|
|
struct mbuf *m;
|
|
|
|
struct fxp_rfa *rfa, *p_rfa;
|
|
|
|
|
|
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
|
|
if (m != NULL) {
|
|
|
|
MCLGET(m, M_DONTWAIT);
|
|
|
|
if ((m->m_flags & M_EXT) == 0) {
|
|
|
|
m_freem(m);
|
1996-09-20 11:05:39 +00:00
|
|
|
if (oldm == NULL)
|
|
|
|
return 1;
|
1995-11-28 23:55:26 +00:00
|
|
|
m = oldm;
|
1996-09-20 11:05:39 +00:00
|
|
|
m->m_data = m->m_ext.ext_buf;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
} else {
|
1996-09-20 11:05:39 +00:00
|
|
|
if (oldm == NULL)
|
|
|
|
return 1;
|
1995-11-28 23:55:26 +00:00
|
|
|
m = oldm;
|
1996-09-20 11:05:39 +00:00
|
|
|
m->m_data = m->m_ext.ext_buf;
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
1997-09-05 10:23:58 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Move the data pointer up so that the incoming data packet
|
|
|
|
* will be 32-bit aligned.
|
|
|
|
*/
|
|
|
|
m->m_data += RFA_ALIGNMENT_FUDGE;
|
|
|
|
|
1996-09-20 11:05:39 +00:00
|
|
|
/*
|
|
|
|
* Get a pointer to the base of the mbuf cluster and move
|
|
|
|
* data start past it.
|
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
rfa = mtod(m, struct fxp_rfa *);
|
1996-09-20 11:05:39 +00:00
|
|
|
m->m_data += sizeof(struct fxp_rfa);
|
1999-09-30 19:03:12 +00:00
|
|
|
rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
|
1996-09-20 11:05:39 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
/*
|
|
|
|
* Initialize the rest of the RFA. Note that since the RFA
|
|
|
|
* is misaligned, we cannot store values directly. Instead,
|
|
|
|
* we use an optimized, inline copy.
|
|
|
|
*/
|
1999-09-30 19:03:12 +00:00
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
rfa->rfa_status = 0;
|
|
|
|
rfa->rfa_control = FXP_RFA_CONTROL_EL;
|
|
|
|
rfa->actual_size = 0;
|
1997-09-05 10:23:58 +00:00
|
|
|
|
|
|
|
v = -1;
|
1999-09-30 19:03:12 +00:00
|
|
|
fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
|
|
|
|
fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
|
1997-09-05 10:23:58 +00:00
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
/*
|
|
|
|
* If there are other buffers already on the list, attach this
|
|
|
|
* one to the end by fixing up the tail to point to this one.
|
|
|
|
*/
|
1995-11-28 23:55:26 +00:00
|
|
|
if (sc->rfa_headm != NULL) {
|
1997-09-05 10:23:58 +00:00
|
|
|
p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
|
|
|
|
RFA_ALIGNMENT_FUDGE);
|
1995-11-28 23:55:26 +00:00
|
|
|
sc->rfa_tailm->m_next = m;
|
1997-09-05 10:23:58 +00:00
|
|
|
v = vtophys(rfa);
|
1999-09-30 19:03:12 +00:00
|
|
|
fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
|
1995-11-28 23:55:26 +00:00
|
|
|
p_rfa->rfa_control &= ~FXP_RFA_CONTROL_EL;
|
|
|
|
} else {
|
|
|
|
sc->rfa_headm = m;
|
|
|
|
}
|
|
|
|
sc->rfa_tailm = m;
|
|
|
|
|
1995-12-01 22:41:56 +00:00
|
|
|
return (m == oldm);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
|
1997-03-21 08:00:13 +00:00
|
|
|
static volatile int
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_mdi_read(sc, phy, reg)
|
|
|
|
struct fxp_softc *sc;
|
1997-03-17 11:08:16 +00:00
|
|
|
int phy;
|
|
|
|
int reg;
|
|
|
|
{
|
|
|
|
int count = 10000;
|
1997-03-21 08:00:13 +00:00
|
|
|
int value;
|
1997-03-17 11:08:16 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
|
|
|
|
(FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
|
1997-03-17 11:08:16 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
|
|
|
|
&& count--)
|
1997-03-21 08:00:13 +00:00
|
|
|
DELAY(10);
|
1997-03-17 11:08:16 +00:00
|
|
|
|
|
|
|
if (count <= 0)
|
1997-09-05 10:23:58 +00:00
|
|
|
printf(FXP_FORMAT ": fxp_mdi_read: timed out\n",
|
|
|
|
FXP_ARGS(sc));
|
1997-03-17 11:08:16 +00:00
|
|
|
|
1997-03-21 08:00:13 +00:00
|
|
|
return (value & 0xffff);
|
1997-03-17 11:08:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
1997-09-05 10:23:58 +00:00
|
|
|
fxp_mdi_write(sc, phy, reg, value)
|
|
|
|
struct fxp_softc *sc;
|
1997-03-17 11:08:16 +00:00
|
|
|
int phy;
|
|
|
|
int reg;
|
|
|
|
int value;
|
|
|
|
{
|
|
|
|
int count = 10000;
|
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
|
|
|
|
(FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
|
|
|
|
(value & 0xffff));
|
1997-03-17 11:08:16 +00:00
|
|
|
|
1997-09-05 10:23:58 +00:00
|
|
|
while((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
|
|
|
|
count--)
|
1997-03-21 08:00:13 +00:00
|
|
|
DELAY(10);
|
1997-03-17 11:08:16 +00:00
|
|
|
|
|
|
|
if (count <= 0)
|
1997-09-05 10:23:58 +00:00
|
|
|
printf(FXP_FORMAT ": fxp_mdi_write: timed out\n",
|
|
|
|
FXP_ARGS(sc));
|
1997-03-17 11:08:16 +00:00
|
|
|
}
|
|
|
|
|
1995-11-28 23:55:26 +00:00
|
|
|
static int
|
|
|
|
fxp_ioctl(ifp, command, data)
|
|
|
|
struct ifnet *ifp;
|
1997-09-05 10:23:58 +00:00
|
|
|
FXP_IOCTLCMD_TYPE command;
|
1995-11-28 23:55:26 +00:00
|
|
|
caddr_t data;
|
|
|
|
{
|
1996-02-06 18:51:28 +00:00
|
|
|
struct fxp_softc *sc = ifp->if_softc;
|
1997-09-05 10:23:58 +00:00
|
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
1995-11-28 23:55:26 +00:00
|
|
|
int s, error = 0;
|
|
|
|
|
|
|
|
s = splimp();
|
|
|
|
|
|
|
|
switch (command) {
|
|
|
|
|
|
|
|
case SIOCSIFADDR:
|
1997-09-05 10:23:58 +00:00
|
|
|
#if !defined(__NetBSD__)
|
1995-11-28 23:55:26 +00:00
|
|
|
case SIOCGIFADDR:
|
1996-12-10 07:29:50 +00:00
|
|
|
case SIOCSIFMTU:
|
1997-09-05 10:23:58 +00:00
|
|
|
#endif
|
1996-12-10 07:29:50 +00:00
|
|
|
error = ether_ioctl(ifp, command, data);
|
1995-11-28 23:55:26 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SIOCSIFFLAGS:
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
|
1995-11-28 23:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If interface is marked up and not running, then start it.
|
|
|
|
* If it is marked down and running, stop it.
|
|
|
|
* XXX If it's up then re-initialize it. This is so flags
|
|
|
|
* such as IFF_PROMISC are handled.
|
|
|
|
*/
|
|
|
|
if (ifp->if_flags & IFF_UP) {
|
1996-12-10 07:29:50 +00:00
|
|
|
fxp_init(sc);
|
1995-11-28 23:55:26 +00:00
|
|
|
} else {
|
|
|
|
if (ifp->if_flags & IFF_RUNNING)
|
1995-12-05 02:01:59 +00:00
|
|
|
fxp_stop(sc);
|
1995-11-28 23:55:26 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIOCADDMULTI:
|
|
|
|
case SIOCDELMULTI:
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
|
1997-09-05 10:23:58 +00:00
|
|
|
#if defined(__NetBSD__)
|
|
|
|
error = (command == SIOCADDMULTI) ?
|
|
|
|
ether_addmulti(ifr, &sc->sc_ethercom) :
|
|
|
|
ether_delmulti(ifr, &sc->sc_ethercom);
|
|
|
|
|
|
|
|
if (error == ENETRESET) {
|
|
|
|
/*
|
|
|
|
* Multicast list has changed; set the hardware
|
|
|
|
* filter accordingly.
|
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
if (!sc->all_mcasts)
|
|
|
|
fxp_mc_setup(sc);
|
|
|
|
/*
|
|
|
|
* fxp_mc_setup() can turn on all_mcasts if we run
|
|
|
|
* out of space, so check it again rather than else {}.
|
|
|
|
*/
|
|
|
|
if (sc->all_mcasts)
|
|
|
|
fxp_init(sc);
|
1997-09-05 10:23:58 +00:00
|
|
|
error = 0;
|
|
|
|
}
|
|
|
|
#else /* __FreeBSD__ */
|
1995-11-28 23:55:26 +00:00
|
|
|
/*
|
1997-01-13 21:26:53 +00:00
|
|
|
* Multicast list has changed; set the hardware filter
|
|
|
|
* accordingly.
|
1995-11-28 23:55:26 +00:00
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
if (!sc->all_mcasts)
|
|
|
|
fxp_mc_setup(sc);
|
|
|
|
/*
|
|
|
|
* fxp_mc_setup() can turn on sc->all_mcasts, so check it
|
|
|
|
* again rather than else {}.
|
|
|
|
*/
|
|
|
|
if (sc->all_mcasts)
|
|
|
|
fxp_init(sc);
|
1997-01-13 21:26:53 +00:00
|
|
|
error = 0;
|
1997-09-05 10:23:58 +00:00
|
|
|
#endif /* __NetBSD__ */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIOCSIFMEDIA:
|
|
|
|
case SIOCGIFMEDIA:
|
|
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
|
1995-11-28 23:55:26 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
error = EINVAL;
|
|
|
|
}
|
|
|
|
(void) splx(s);
|
|
|
|
return (error);
|
|
|
|
}
|
1997-09-29 11:27:43 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Program the multicast filter.
|
|
|
|
*
|
|
|
|
* We have an artificial restriction that the multicast setup command
|
|
|
|
* must be the first command in the chain, so we take steps to ensure
|
1998-08-04 08:53:12 +00:00
|
|
|
* this. By requiring this, it allows us to keep up the performance of
|
1997-09-29 11:27:43 +00:00
|
|
|
* the pre-initialized command ring (esp. link pointers) by not actually
|
1998-04-17 22:37:19 +00:00
|
|
|
* inserting the mcsetup command in the ring - i.e. its link pointer
|
1997-09-29 11:27:43 +00:00
|
|
|
* points to the TxCB ring, but the mcsetup descriptor itself is not part
|
|
|
|
* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
|
|
|
|
* lead into the regular TxCB ring when it completes.
|
|
|
|
*
|
|
|
|
* This function must be called at splimp.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
fxp_mc_setup(sc)
|
|
|
|
struct fxp_softc *sc;
|
|
|
|
{
|
|
|
|
struct fxp_cb_mcs *mcsp = sc->mcsp;
|
|
|
|
struct ifnet *ifp = &sc->sc_if;
|
|
|
|
struct ifmultiaddr *ifma;
|
|
|
|
int nmcasts;
|
|
|
|
|
1998-08-04 08:53:12 +00:00
|
|
|
/*
|
|
|
|
* If there are queued commands, we must wait until they are all
|
|
|
|
* completed. If we are already waiting, then add a NOP command
|
|
|
|
* with interrupt option so that we're notified when all commands
|
|
|
|
* have been completed - fxp_start() ensures that no additional
|
|
|
|
* TX commands will be added when need_mcsetup is true.
|
|
|
|
*/
|
1997-09-29 11:27:43 +00:00
|
|
|
if (sc->tx_queued) {
|
1998-08-04 08:53:12 +00:00
|
|
|
struct fxp_cb_tx *txp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* need_mcsetup will be true if we are already waiting for the
|
|
|
|
* NOP command to be completed (see below). In this case, bail.
|
|
|
|
*/
|
|
|
|
if (sc->need_mcsetup)
|
|
|
|
return;
|
1997-09-29 11:27:43 +00:00
|
|
|
sc->need_mcsetup = 1;
|
1998-08-04 08:53:12 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Add a NOP command with interrupt so that we are notified when all
|
|
|
|
* TX commands have been processed.
|
|
|
|
*/
|
|
|
|
txp = sc->cbl_last->next;
|
|
|
|
txp->mb_head = NULL;
|
|
|
|
txp->cb_status = 0;
|
|
|
|
txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
|
|
|
|
/*
|
|
|
|
* Advance the end of list forward.
|
|
|
|
*/
|
|
|
|
sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
|
|
|
|
sc->cbl_last = txp;
|
|
|
|
sc->tx_queued++;
|
|
|
|
/*
|
|
|
|
* Issue a resume in case the CU has just suspended.
|
|
|
|
*/
|
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_RESUME);
|
|
|
|
/*
|
|
|
|
* Set a 5 second timer just in case we don't hear from the
|
|
|
|
* card again.
|
|
|
|
*/
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
|
1997-09-29 11:27:43 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
sc->need_mcsetup = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize multicast setup descriptor.
|
|
|
|
*/
|
|
|
|
mcsp->next = sc->cbl_base;
|
|
|
|
mcsp->mb_head = NULL;
|
|
|
|
mcsp->cb_status = 0;
|
1998-08-04 08:53:12 +00:00
|
|
|
mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
|
1997-09-29 11:27:43 +00:00
|
|
|
mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
|
|
|
|
|
|
|
|
nmcasts = 0;
|
|
|
|
if (!sc->all_mcasts) {
|
|
|
|
for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
|
|
|
|
ifma = ifma->ifma_link.le_next) {
|
|
|
|
if (ifma->ifma_addr->sa_family != AF_LINK)
|
|
|
|
continue;
|
|
|
|
if (nmcasts >= MAXMCADDR) {
|
|
|
|
sc->all_mcasts = 1;
|
|
|
|
nmcasts = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
|
1999-01-28 00:57:57 +00:00
|
|
|
(volatile void *) &sc->mcsp->mc_addr[nmcasts][0], 6);
|
1997-09-29 11:27:43 +00:00
|
|
|
nmcasts++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
mcsp->mc_cnt = nmcasts * 6;
|
|
|
|
sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
|
|
|
|
sc->tx_queued = 1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait until command unit is not active. This should never
|
|
|
|
* be the case when nothing is queued, but make sure anyway.
|
|
|
|
*/
|
|
|
|
while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
|
|
|
|
FXP_SCB_CUS_ACTIVE) ;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start the multicast setup command.
|
|
|
|
*/
|
|
|
|
fxp_scb_wait(sc);
|
|
|
|
CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
|
|
|
|
CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_SCB_COMMAND_CU_START);
|
|
|
|
|
1998-08-04 08:53:12 +00:00
|
|
|
ifp->if_timer = 2;
|
1997-09-29 11:27:43 +00:00
|
|
|
return;
|
|
|
|
}
|