2005-01-05 20:17:21 +00:00
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/*-
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2017-11-27 15:11:47 +00:00
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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1997-04-26 11:46:25 +00:00
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* Copyright (c) 1996, by Peter Wemm and Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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1999-08-28 01:08:13 +00:00
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* $FreeBSD$
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1997-04-26 11:46:25 +00:00
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*/
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2010-11-01 18:18:46 +00:00
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#ifndef _X86_APICREG_H_
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#define _X86_APICREG_H_
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1997-04-26 11:46:25 +00:00
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/*
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* Local && I/O APIC definitions.
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*/
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/*
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2003-08-15 15:23:13 +00:00
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* Pentium P54C+ Built-in APIC
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1997-04-26 11:46:25 +00:00
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* (Advanced programmable Interrupt Controller)
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*
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2003-08-15 15:23:13 +00:00
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* Base Address of Built-in APIC in memory location
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1997-04-26 11:46:25 +00:00
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* is 0xfee00000.
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*
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2003-09-10 01:11:58 +00:00
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* Map of APIC Registers:
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1997-04-26 11:46:25 +00:00
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*
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* Offset (hex) Description Read/Write state
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* 000 Reserved
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* 010 Reserved
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* 020 ID Local APIC ID R/W
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* 030 VER Local APIC Version R
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* 040 Reserved
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* 050 Reserved
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* 060 Reserved
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* 070 Reserved
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* 080 Task Priority Register R/W
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* 090 Arbitration Priority Register R
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* 0A0 Processor Priority Register R
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* 0B0 EOI Register W
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* 0C0 RRR Remote read R
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* 0D0 Logical Destination R/W
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* 0E0 Destination Format Register 0..27 R; 28..31 R/W
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* 0F0 SVR Spurious Interrupt Vector Reg. 0..3 R; 4..9 R/W
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* 100 ISR 000-031 R
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* 110 ISR 032-063 R
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* 120 ISR 064-095 R
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* 130 ISR 095-128 R
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* 140 ISR 128-159 R
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* 150 ISR 160-191 R
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* 160 ISR 192-223 R
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* 170 ISR 224-255 R
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* 180 TMR 000-031 R
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* 190 TMR 032-063 R
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* 1A0 TMR 064-095 R
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* 1B0 TMR 095-128 R
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* 1C0 TMR 128-159 R
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* 1D0 TMR 160-191 R
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* 1E0 TMR 192-223 R
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* 1F0 TMR 224-255 R
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* 200 IRR 000-031 R
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* 210 IRR 032-063 R
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* 220 IRR 064-095 R
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* 230 IRR 095-128 R
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* 240 IRR 128-159 R
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* 250 IRR 160-191 R
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* 260 IRR 192-223 R
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* 270 IRR 224-255 R
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* 280 Error Status Register R
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* 290 Reserved
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* 2A0 Reserved
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* 2B0 Reserved
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* 2C0 Reserved
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* 2D0 Reserved
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* 2E0 Reserved
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2010-05-24 15:45:05 +00:00
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* 2F0 Local Vector Table (CMCI) R/W
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1997-04-26 11:46:25 +00:00
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* 300 ICR_LOW Interrupt Command Reg. (0-31) R/W
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* 310 ICR_HI Interrupt Command Reg. (32-63) R/W
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* 320 Local Vector Table (Timer) R/W
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2003-06-06 17:22:15 +00:00
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* 330 Local Vector Table (Thermal) R/W (PIV+)
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* 340 Local Vector Table (Performance) R/W (P6+)
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1997-04-26 11:46:25 +00:00
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* 350 LVT1 Local Vector Table (LINT0) R/W
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* 360 LVT2 Local Vector Table (LINT1) R/W
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* 370 LVT3 Local Vector Table (ERROR) R/W
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* 380 Initial Count Reg. for Timer R/W
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* 390 Current Count of Timer R
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* 3A0 Reserved
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* 3B0 Reserved
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* 3C0 Reserved
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* 3D0 Reserved
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* 3E0 Timer Divide Configuration Reg. R/W
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* 3F0 Reserved
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*/
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/******************************************************************************
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* global defines, etc.
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*/
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1997-05-29 05:57:43 +00:00
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/******************************************************************************
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* LOCAL APIC structure
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*/
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#ifndef LOCORE
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#include <sys/types.h>
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#define PAD3 int : 32; int : 32; int : 32
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#define PAD4 int : 32; int : 32; int : 32; int : 32
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struct LAPIC {
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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u_int32_t id; PAD3;
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u_int32_t version; PAD3;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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u_int32_t tpr; PAD3;
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u_int32_t apr; PAD3;
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u_int32_t ppr; PAD3;
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u_int32_t eoi; PAD3;
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/* reserved */ PAD4;
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u_int32_t ldr; PAD3;
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u_int32_t dfr; PAD3;
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u_int32_t svr; PAD3;
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u_int32_t isr0; PAD3;
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u_int32_t isr1; PAD3;
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u_int32_t isr2; PAD3;
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u_int32_t isr3; PAD3;
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u_int32_t isr4; PAD3;
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u_int32_t isr5; PAD3;
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u_int32_t isr6; PAD3;
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u_int32_t isr7; PAD3;
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u_int32_t tmr0; PAD3;
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u_int32_t tmr1; PAD3;
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u_int32_t tmr2; PAD3;
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u_int32_t tmr3; PAD3;
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u_int32_t tmr4; PAD3;
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u_int32_t tmr5; PAD3;
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u_int32_t tmr6; PAD3;
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u_int32_t tmr7; PAD3;
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u_int32_t irr0; PAD3;
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u_int32_t irr1; PAD3;
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u_int32_t irr2; PAD3;
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u_int32_t irr3; PAD3;
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u_int32_t irr4; PAD3;
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u_int32_t irr5; PAD3;
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u_int32_t irr6; PAD3;
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u_int32_t irr7; PAD3;
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u_int32_t esr; PAD3;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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2010-05-24 15:45:05 +00:00
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u_int32_t lvt_cmci; PAD3;
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1997-05-29 05:57:43 +00:00
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u_int32_t icr_lo; PAD3;
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u_int32_t icr_hi; PAD3;
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u_int32_t lvt_timer; PAD3;
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2003-06-06 17:22:15 +00:00
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u_int32_t lvt_thermal; PAD3;
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1997-05-29 05:57:43 +00:00
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u_int32_t lvt_pcint; PAD3;
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u_int32_t lvt_lint0; PAD3;
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u_int32_t lvt_lint1; PAD3;
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u_int32_t lvt_error; PAD3;
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u_int32_t icr_timer; PAD3;
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u_int32_t ccr_timer; PAD3;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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/* reserved */ PAD4;
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u_int32_t dcr_timer; PAD3;
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/* reserved */ PAD4;
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};
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typedef struct LAPIC lapic_t;
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2015-02-09 21:00:56 +00:00
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enum LAPIC_REGISTERS {
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LAPIC_ID = 0x2,
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LAPIC_VERSION = 0x3,
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LAPIC_TPR = 0x8,
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LAPIC_APR = 0x9,
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LAPIC_PPR = 0xa,
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LAPIC_EOI = 0xb,
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LAPIC_LDR = 0xd,
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LAPIC_DFR = 0xe, /* Not in x2APIC */
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LAPIC_SVR = 0xf,
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LAPIC_ISR0 = 0x10,
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LAPIC_ISR1 = 0x11,
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LAPIC_ISR2 = 0x12,
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LAPIC_ISR3 = 0x13,
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LAPIC_ISR4 = 0x14,
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LAPIC_ISR5 = 0x15,
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LAPIC_ISR6 = 0x16,
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LAPIC_ISR7 = 0x17,
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LAPIC_TMR0 = 0x18,
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LAPIC_TMR1 = 0x19,
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LAPIC_TMR2 = 0x1a,
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LAPIC_TMR3 = 0x1b,
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LAPIC_TMR4 = 0x1c,
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LAPIC_TMR5 = 0x1d,
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LAPIC_TMR6 = 0x1e,
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LAPIC_TMR7 = 0x1f,
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LAPIC_IRR0 = 0x20,
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LAPIC_IRR1 = 0x21,
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LAPIC_IRR2 = 0x22,
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LAPIC_IRR3 = 0x23,
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LAPIC_IRR4 = 0x24,
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LAPIC_IRR5 = 0x25,
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LAPIC_IRR6 = 0x26,
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LAPIC_IRR7 = 0x27,
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LAPIC_ESR = 0x28,
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LAPIC_LVT_CMCI = 0x2f,
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LAPIC_ICR_LO = 0x30,
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LAPIC_ICR_HI = 0x31, /* Not in x2APIC */
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LAPIC_LVT_TIMER = 0x32,
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LAPIC_LVT_THERMAL = 0x33,
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LAPIC_LVT_PCINT = 0x34,
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LAPIC_LVT_LINT0 = 0x35,
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LAPIC_LVT_LINT1 = 0x36,
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LAPIC_LVT_ERROR = 0x37,
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LAPIC_ICR_TIMER = 0x38,
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LAPIC_CCR_TIMER = 0x39,
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LAPIC_DCR_TIMER = 0x3e,
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LAPIC_SELF_IPI = 0x3f, /* Only in x2APIC */
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2017-02-28 18:48:12 +00:00
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LAPIC_EXT_FEATURES = 0x40, /* AMD */
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LAPIC_EXT_CTRL = 0x41, /* AMD */
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LAPIC_EXT_SEOI = 0x42, /* AMD */
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LAPIC_EXT_IER0 = 0x48, /* AMD */
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LAPIC_EXT_IER1 = 0x49, /* AMD */
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LAPIC_EXT_IER2 = 0x4a, /* AMD */
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LAPIC_EXT_IER3 = 0x4b, /* AMD */
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LAPIC_EXT_IER4 = 0x4c, /* AMD */
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LAPIC_EXT_IER5 = 0x4d, /* AMD */
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LAPIC_EXT_IER6 = 0x4e, /* AMD */
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LAPIC_EXT_IER7 = 0x4f, /* AMD */
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LAPIC_EXT_LVT0 = 0x50, /* AMD */
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LAPIC_EXT_LVT1 = 0x51, /* AMD */
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LAPIC_EXT_LVT2 = 0x52, /* AMD */
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LAPIC_EXT_LVT3 = 0x53, /* AMD */
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2015-02-09 21:00:56 +00:00
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};
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2017-02-28 18:48:12 +00:00
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#define LAPIC_MEM_MUL 0x10
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2015-02-09 21:00:56 +00:00
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/*
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2017-02-28 18:48:12 +00:00
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* Although some registers are available on AMD processors only,
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* it's not a big waste to reserve them on all platforms.
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* However, we need to watch out for this space being assigned for
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* non-APIC purposes in the future processor models.
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2015-02-09 21:00:56 +00:00
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*/
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2017-02-28 18:48:12 +00:00
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#define LAPIC_MEM_REGION ((LAPIC_EXT_LVT3 + 1) * LAPIC_MEM_MUL)
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2015-02-09 21:00:56 +00:00
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1997-05-29 05:57:43 +00:00
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/******************************************************************************
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* I/O APIC structure
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*/
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struct IOAPIC {
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u_int32_t ioregsel; PAD3;
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u_int32_t iowin; PAD3;
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};
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typedef struct IOAPIC ioapic_t;
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#undef PAD4
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#undef PAD3
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1997-07-15 02:47:54 +00:00
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#endif /* !LOCORE */
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/******************************************************************************
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* various code 'logical' values
|
|
|
|
|
*/
|
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|
1997-04-26 11:46:25 +00:00
|
|
|
/******************************************************************************
|
|
|
|
|
* LOCAL APIC defines
|
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|
|
|
*/
|
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|
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|
|
|
|
|
|
/* default physical locations of LOCAL (CPU) APICs */
|
|
|
|
|
#define DEFAULT_APIC_BASE 0xfee00000
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|
2003-11-03 21:53:38 +00:00
|
|
|
/* constants relating to APIC ID registers */
|
|
|
|
|
#define APIC_ID_MASK 0xff000000
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|
|
#define APIC_ID_SHIFT 24
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|
#define APIC_ID_CLUSTER 0xf0
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|
#define APIC_ID_CLUSTER_ID 0x0f
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|
#define APIC_MAX_CLUSTER 0xe
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|
#define APIC_MAX_INTRACLUSTER_ID 3
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|
#define APIC_ID_CLUSTER_SHIFT 4
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|
1997-04-26 11:46:25 +00:00
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|
/* fields in VER */
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|
#define APIC_VER_VERSION 0x000000ff
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|
#define APIC_VER_MAXLVT 0x00ff0000
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|
#define MAXLVTSHIFT 16
|
2010-05-19 19:52:41 +00:00
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|
#define APIC_VER_EOI_SUPPRESSION 0x01000000
|
2017-02-28 18:48:12 +00:00
|
|
|
#define APIC_VER_AMD_EXT_SPACE 0x80000000
|
1997-04-26 11:46:25 +00:00
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|
2003-11-03 21:53:38 +00:00
|
|
|
/* fields in LDR */
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|
|
#define APIC_LDR_RESERVED 0x00ffffff
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/* fields in DFR */
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|
#define APIC_DFR_RESERVED 0x0fffffff
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#define APIC_DFR_MODEL_MASK 0xf0000000
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#define APIC_DFR_MODEL_FLAT 0xf0000000
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|
#define APIC_DFR_MODEL_CLUSTER 0x00000000
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|
1997-04-26 11:46:25 +00:00
|
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|
/* fields in SVR */
|
1997-07-08 23:32:58 +00:00
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#define APIC_SVR_VECTOR 0x000000ff
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#define APIC_SVR_VEC_PROG 0x000000f0
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#define APIC_SVR_VEC_FIX 0x0000000f
|
1997-04-26 11:46:25 +00:00
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|
#define APIC_SVR_ENABLE 0x00000100
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# define APIC_SVR_SWDIS 0x00000000
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# define APIC_SVR_SWEN 0x00000100
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#define APIC_SVR_FOCUS 0x00000200
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|
# define APIC_SVR_FEN 0x00000000
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|
# define APIC_SVR_FDIS 0x00000200
|
2010-05-19 19:52:41 +00:00
|
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|
#define APIC_SVR_EOI_SUPPRESSION 0x00001000
|
1997-07-08 23:32:58 +00:00
|
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|
|
/* fields in TPR */
|
1997-04-26 11:46:25 +00:00
|
|
|
#define APIC_TPR_PRIO 0x000000ff
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|
|
# define APIC_TPR_INT 0x000000f0
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|
|
# define APIC_TPR_SUB 0x0000000f
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|
|
2008-12-11 15:56:30 +00:00
|
|
|
/* fields in ESR */
|
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|
|
|
#define APIC_ESR_SEND_CS_ERROR 0x00000001
|
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|
|
#define APIC_ESR_RECEIVE_CS_ERROR 0x00000002
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|
|
#define APIC_ESR_SEND_ACCEPT 0x00000004
|
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|
|
#define APIC_ESR_RECEIVE_ACCEPT 0x00000008
|
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|
|
#define APIC_ESR_SEND_ILLEGAL_VECTOR 0x00000020
|
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|
|
#define APIC_ESR_RECEIVE_ILLEGAL_VECTOR 0x00000040
|
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|
|
#define APIC_ESR_ILLEGAL_REGISTER 0x00000080
|
1997-04-26 11:46:25 +00:00
|
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|
|
|
|
|
|
/* fields in ICR_LOW */
|
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|
|
|
#define APIC_VECTOR_MASK 0x000000ff
|
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|
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|
|
#define APIC_DELMODE_MASK 0x00000700
|
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|
|
|
# define APIC_DELMODE_FIXED 0x00000000
|
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|
|
# define APIC_DELMODE_LOWPRIO 0x00000100
|
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|
|
# define APIC_DELMODE_SMI 0x00000200
|
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|
|
|
# define APIC_DELMODE_RR 0x00000300
|
|
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|
|
# define APIC_DELMODE_NMI 0x00000400
|
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|
|
# define APIC_DELMODE_INIT 0x00000500
|
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|
|
# define APIC_DELMODE_STARTUP 0x00000600
|
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|
|
# define APIC_DELMODE_RESV 0x00000700
|
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|
|
|
|
|
|
|
|
#define APIC_DESTMODE_MASK 0x00000800
|
|
|
|
|
# define APIC_DESTMODE_PHY 0x00000000
|
|
|
|
|
# define APIC_DESTMODE_LOG 0x00000800
|
|
|
|
|
|
|
|
|
|
#define APIC_DELSTAT_MASK 0x00001000
|
|
|
|
|
# define APIC_DELSTAT_IDLE 0x00000000
|
|
|
|
|
# define APIC_DELSTAT_PEND 0x00001000
|
|
|
|
|
|
|
|
|
|
#define APIC_RESV1_MASK 0x00002000
|
|
|
|
|
|
|
|
|
|
#define APIC_LEVEL_MASK 0x00004000
|
|
|
|
|
# define APIC_LEVEL_DEASSERT 0x00000000
|
|
|
|
|
# define APIC_LEVEL_ASSERT 0x00004000
|
|
|
|
|
|
|
|
|
|
#define APIC_TRIGMOD_MASK 0x00008000
|
|
|
|
|
# define APIC_TRIGMOD_EDGE 0x00000000
|
|
|
|
|
# define APIC_TRIGMOD_LEVEL 0x00008000
|
|
|
|
|
|
|
|
|
|
#define APIC_RRSTAT_MASK 0x00030000
|
|
|
|
|
# define APIC_RRSTAT_INVALID 0x00000000
|
|
|
|
|
# define APIC_RRSTAT_INPROG 0x00010000
|
|
|
|
|
# define APIC_RRSTAT_VALID 0x00020000
|
|
|
|
|
# define APIC_RRSTAT_RESV 0x00030000
|
|
|
|
|
|
|
|
|
|
#define APIC_DEST_MASK 0x000c0000
|
|
|
|
|
# define APIC_DEST_DESTFLD 0x00000000
|
|
|
|
|
# define APIC_DEST_SELF 0x00040000
|
|
|
|
|
# define APIC_DEST_ALLISELF 0x00080000
|
|
|
|
|
# define APIC_DEST_ALLESELF 0x000c0000
|
|
|
|
|
|
|
|
|
|
#define APIC_RESV2_MASK 0xfff00000
|
|
|
|
|
|
2003-07-23 18:59:38 +00:00
|
|
|
#define APIC_ICRLO_RESV_MASK (APIC_RESV1_MASK | APIC_RESV2_MASK)
|
1997-04-26 11:46:25 +00:00
|
|
|
|
|
|
|
|
/* fields in LVT1/2 */
|
|
|
|
|
#define APIC_LVT_VECTOR 0x000000ff
|
1997-06-27 22:13:50 +00:00
|
|
|
#define APIC_LVT_DM 0x00000700
|
|
|
|
|
# define APIC_LVT_DM_FIXED 0x00000000
|
2003-06-06 17:22:15 +00:00
|
|
|
# define APIC_LVT_DM_SMI 0x00000200
|
1997-06-27 22:13:50 +00:00
|
|
|
# define APIC_LVT_DM_NMI 0x00000400
|
2003-06-06 17:22:15 +00:00
|
|
|
# define APIC_LVT_DM_INIT 0x00000500
|
1997-06-27 22:13:50 +00:00
|
|
|
# define APIC_LVT_DM_EXTINT 0x00000700
|
1997-04-26 11:46:25 +00:00
|
|
|
#define APIC_LVT_DS 0x00001000
|
1997-06-27 22:13:50 +00:00
|
|
|
#define APIC_LVT_IIPP 0x00002000
|
|
|
|
|
#define APIC_LVT_IIPP_INTALO 0x00002000
|
|
|
|
|
#define APIC_LVT_IIPP_INTAHI 0x00000000
|
|
|
|
|
#define APIC_LVT_RIRR 0x00004000
|
|
|
|
|
#define APIC_LVT_TM 0x00008000
|
1997-04-26 11:46:25 +00:00
|
|
|
#define APIC_LVT_M 0x00010000
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* fields in LVT Timer */
|
|
|
|
|
#define APIC_LVTT_VECTOR 0x000000ff
|
|
|
|
|
#define APIC_LVTT_DS 0x00001000
|
|
|
|
|
#define APIC_LVTT_M 0x00010000
|
2016-03-28 09:43:40 +00:00
|
|
|
#define APIC_LVTT_TM 0x00060000
|
2005-01-21 06:01:20 +00:00
|
|
|
# define APIC_LVTT_TM_ONE_SHOT 0x00000000
|
|
|
|
|
# define APIC_LVTT_TM_PERIODIC 0x00020000
|
2016-03-28 09:43:40 +00:00
|
|
|
# define APIC_LVTT_TM_TSCDLT 0x00040000
|
|
|
|
|
# define APIC_LVTT_TM_RSRV 0x00060000
|
1997-04-26 11:46:25 +00:00
|
|
|
|
2005-01-21 06:01:20 +00:00
|
|
|
/* APIC timer current count */
|
|
|
|
|
#define APIC_TIMER_MAX_COUNT 0xffffffff
|
|
|
|
|
|
1997-04-26 11:46:25 +00:00
|
|
|
/* fields in TDCR */
|
|
|
|
|
#define APIC_TDCR_2 0x00
|
|
|
|
|
#define APIC_TDCR_4 0x01
|
|
|
|
|
#define APIC_TDCR_8 0x02
|
|
|
|
|
#define APIC_TDCR_16 0x03
|
|
|
|
|
#define APIC_TDCR_32 0x08
|
|
|
|
|
#define APIC_TDCR_64 0x09
|
|
|
|
|
#define APIC_TDCR_128 0x0a
|
|
|
|
|
#define APIC_TDCR_1 0x0b
|
|
|
|
|
|
2017-02-28 18:48:12 +00:00
|
|
|
/* Constants related to AMD Extended APIC Features Register */
|
|
|
|
|
#define APIC_EXTF_ELVT_MASK 0x00ff0000
|
|
|
|
|
#define APIC_EXTF_ELVT_SHIFT 16
|
|
|
|
|
#define APIC_EXTF_EXTID_CAP 0x00000004
|
|
|
|
|
#define APIC_EXTF_SEIO_CAP 0x00000002
|
|
|
|
|
#define APIC_EXTF_IER_CAP 0x00000001
|
|
|
|
|
|
2013-12-09 21:08:52 +00:00
|
|
|
/* LVT table indices */
|
|
|
|
|
#define APIC_LVT_LINT0 0
|
|
|
|
|
#define APIC_LVT_LINT1 1
|
|
|
|
|
#define APIC_LVT_TIMER 2
|
|
|
|
|
#define APIC_LVT_ERROR 3
|
|
|
|
|
#define APIC_LVT_PMC 4
|
|
|
|
|
#define APIC_LVT_THERMAL 5
|
|
|
|
|
#define APIC_LVT_CMCI 6
|
|
|
|
|
#define APIC_LVT_MAX APIC_LVT_CMCI
|
|
|
|
|
|
2017-02-28 18:48:12 +00:00
|
|
|
/* AMD extended LVT constants, seem to be assigned by fiat */
|
|
|
|
|
#define APIC_ELVT_IBS 0 /* Instruction based sampling */
|
|
|
|
|
#define APIC_ELVT_MCA 1 /* MCE thresholding */
|
|
|
|
|
#define APIC_ELVT_DEI 2 /* Deferred error interrupt */
|
|
|
|
|
#define APIC_ELVT_SBI 3 /* Sideband interface */
|
|
|
|
|
#define APIC_ELVT_MAX APIC_ELVT_SBI
|
|
|
|
|
|
1997-04-26 11:46:25 +00:00
|
|
|
/******************************************************************************
|
|
|
|
|
* I/O APIC defines
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* default physical locations of an IO APIC */
|
|
|
|
|
#define DEFAULT_IO_APIC_BASE 0xfec00000
|
|
|
|
|
|
|
|
|
|
/* window register offset */
|
|
|
|
|
#define IOAPIC_WINDOW 0x10
|
2010-05-19 19:52:41 +00:00
|
|
|
#define IOAPIC_EOIR 0x40
|
1997-04-26 11:46:25 +00:00
|
|
|
|
2017-09-08 19:25:11 +00:00
|
|
|
#define IOAPIC_WND_SIZE 0x50
|
|
|
|
|
|
1997-04-26 11:46:25 +00:00
|
|
|
/* indexes into IO APIC */
|
|
|
|
|
#define IOAPIC_ID 0x00
|
|
|
|
|
#define IOAPIC_VER 0x01
|
|
|
|
|
#define IOAPIC_ARB 0x02
|
|
|
|
|
#define IOAPIC_REDTBL 0x10
|
|
|
|
|
#define IOAPIC_REDTBL0 IOAPIC_REDTBL
|
|
|
|
|
#define IOAPIC_REDTBL1 (IOAPIC_REDTBL+0x02)
|
|
|
|
|
#define IOAPIC_REDTBL2 (IOAPIC_REDTBL+0x04)
|
|
|
|
|
#define IOAPIC_REDTBL3 (IOAPIC_REDTBL+0x06)
|
|
|
|
|
#define IOAPIC_REDTBL4 (IOAPIC_REDTBL+0x08)
|
|
|
|
|
#define IOAPIC_REDTBL5 (IOAPIC_REDTBL+0x0a)
|
|
|
|
|
#define IOAPIC_REDTBL6 (IOAPIC_REDTBL+0x0c)
|
|
|
|
|
#define IOAPIC_REDTBL7 (IOAPIC_REDTBL+0x0e)
|
|
|
|
|
#define IOAPIC_REDTBL8 (IOAPIC_REDTBL+0x10)
|
|
|
|
|
#define IOAPIC_REDTBL9 (IOAPIC_REDTBL+0x12)
|
|
|
|
|
#define IOAPIC_REDTBL10 (IOAPIC_REDTBL+0x14)
|
|
|
|
|
#define IOAPIC_REDTBL11 (IOAPIC_REDTBL+0x16)
|
|
|
|
|
#define IOAPIC_REDTBL12 (IOAPIC_REDTBL+0x18)
|
|
|
|
|
#define IOAPIC_REDTBL13 (IOAPIC_REDTBL+0x1a)
|
|
|
|
|
#define IOAPIC_REDTBL14 (IOAPIC_REDTBL+0x1c)
|
|
|
|
|
#define IOAPIC_REDTBL15 (IOAPIC_REDTBL+0x1e)
|
|
|
|
|
#define IOAPIC_REDTBL16 (IOAPIC_REDTBL+0x20)
|
|
|
|
|
#define IOAPIC_REDTBL17 (IOAPIC_REDTBL+0x22)
|
|
|
|
|
#define IOAPIC_REDTBL18 (IOAPIC_REDTBL+0x24)
|
|
|
|
|
#define IOAPIC_REDTBL19 (IOAPIC_REDTBL+0x26)
|
|
|
|
|
#define IOAPIC_REDTBL20 (IOAPIC_REDTBL+0x28)
|
|
|
|
|
#define IOAPIC_REDTBL21 (IOAPIC_REDTBL+0x2a)
|
|
|
|
|
#define IOAPIC_REDTBL22 (IOAPIC_REDTBL+0x2c)
|
|
|
|
|
#define IOAPIC_REDTBL23 (IOAPIC_REDTBL+0x2e)
|
|
|
|
|
|
|
|
|
|
/* fields in VER */
|
|
|
|
|
#define IOART_VER_VERSION 0x000000ff
|
|
|
|
|
#define IOART_VER_MAXREDIR 0x00ff0000
|
|
|
|
|
#define MAXREDIRSHIFT 16
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* fields in the IO APIC's redirection table entries
|
|
|
|
|
*/
|
|
|
|
|
#define IOART_DEST APIC_ID_MASK /* broadcast addr: all APICs */
|
|
|
|
|
|
|
|
|
|
#define IOART_RESV 0x00fe0000 /* reserved */
|
|
|
|
|
|
|
|
|
|
#define IOART_INTMASK 0x00010000 /* R/W: INTerrupt mask */
|
|
|
|
|
# define IOART_INTMCLR 0x00000000 /* clear, allow INTs */
|
|
|
|
|
# define IOART_INTMSET 0x00010000 /* set, inhibit INTs */
|
|
|
|
|
|
|
|
|
|
#define IOART_TRGRMOD 0x00008000 /* R/W: trigger mode */
|
|
|
|
|
# define IOART_TRGREDG 0x00000000 /* edge */
|
|
|
|
|
# define IOART_TRGRLVL 0x00008000 /* level */
|
|
|
|
|
|
|
|
|
|
#define IOART_REM_IRR 0x00004000 /* RO: remote IRR */
|
|
|
|
|
|
|
|
|
|
#define IOART_INTPOL 0x00002000 /* R/W: INT input pin polarity */
|
|
|
|
|
# define IOART_INTAHI 0x00000000 /* active high */
|
|
|
|
|
# define IOART_INTALO 0x00002000 /* active low */
|
|
|
|
|
|
|
|
|
|
#define IOART_DELIVS 0x00001000 /* RO: delivery status */
|
|
|
|
|
|
|
|
|
|
#define IOART_DESTMOD 0x00000800 /* R/W: destination mode */
|
|
|
|
|
# define IOART_DESTPHY 0x00000000 /* physical */
|
|
|
|
|
# define IOART_DESTLOG 0x00000800 /* logical */
|
|
|
|
|
|
|
|
|
|
#define IOART_DELMOD 0x00000700 /* R/W: delivery mode */
|
|
|
|
|
# define IOART_DELFIXED 0x00000000 /* fixed */
|
|
|
|
|
# define IOART_DELLOPRI 0x00000100 /* lowest priority */
|
|
|
|
|
# define IOART_DELSMI 0x00000200 /* System Management INT */
|
|
|
|
|
# define IOART_DELRSV1 0x00000300 /* reserved */
|
|
|
|
|
# define IOART_DELNMI 0x00000400 /* NMI signal */
|
|
|
|
|
# define IOART_DELINIT 0x00000500 /* INIT signal */
|
|
|
|
|
# define IOART_DELRSV2 0x00000600 /* reserved */
|
|
|
|
|
# define IOART_DELEXINT 0x00000700 /* External INTerrupt */
|
|
|
|
|
|
|
|
|
|
#define IOART_INTVEC 0x000000ff /* R/W: INTerrupt vector field */
|
|
|
|
|
|
2010-11-01 18:18:46 +00:00
|
|
|
#endif /* _X86_APICREG_H_ */
|
