d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
c73f51f840
freebsd-skq/sys/mips/atheros/ar934x_chip.c

475 lines
12 KiB
C
Raw Normal View History

Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
/*-
* Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <net/ethernet.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include <machine/hwfunc.h>
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/atheros/ar71xxreg.h>
#include <mips/atheros/ar934xreg.h>
#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/atheros/ar71xx_setup.h>
#include <mips/atheros/ar71xx_chip.h>
#include <mips/atheros/ar934x_chip.h>
static void
ar934x_chip_detect_mem_size(void)
{
}
static uint32_t
ar934x_get_pll_freq(uint32_t ref, uint32_t ref_div, uint32_t nint,
uint32_t nfrac, uint32_t frac, uint32_t out_div)
{
uint64_t t;
uint32_t ret;
t = u_ar71xx_refclk;
t *= nint;
t = t / ref_div;
ret = t;
t = u_ar71xx_refclk;
t *= nfrac;
t = t / (ref_div * frac);
ret += t;
ret /= (1 << out_div);
return (ret);
}
static void
ar934x_chip_detect_sys_frequency(void)
{
uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
uint32_t cpu_pll, ddr_pll;
uint32_t bootstrap;
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
uint32_t reg;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
bootstrap = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
u_ar71xx_refclk = 40 * 1000 * 1000;
else
u_ar71xx_refclk = 25 * 1000 * 1000;
pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
AR934X_SRIF_DPLL2_OUTDIV_MASK;
pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG);
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
AR934X_SRIF_DPLL1_NINT_MASK;
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG);
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR934X_PLL_CPU_CONFIG_NINT_MASK;
nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
frac = 1 << 6;
}
cpu_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
nfrac, frac, out_div);
pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
AR934X_SRIF_DPLL2_OUTDIV_MASK;
pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG);
nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
AR934X_SRIF_DPLL1_NINT_MASK;
nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG);
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
AR934X_PLL_DDR_CONFIG_NINT_MASK;
nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
frac = 1 << 10;
}
ddr_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
nfrac, frac, out_div);
clk_ctrl = ATH_READ_REG(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
u_ar71xx_cpu_freq = u_ar71xx_refclk;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
u_ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
else
u_ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
u_ar71xx_ddr_freq = u_ar71xx_refclk;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
u_ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
else
u_ar71xx_ddr_freq = cpu_pll / (postdiv + 1);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
u_ar71xx_ahb_freq = u_ar71xx_refclk;
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
u_ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
else
u_ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
u_ar71xx_wdt_freq = u_ar71xx_refclk;
u_ar71xx_uart_freq = u_ar71xx_refclk;
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
/*
* Next, fetch reference clock speed for MDIO bus.
*/
reg = ATH_READ_REG(AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
if (reg & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
printf("%s: mdio=100MHz\n", __func__);
u_ar71xx_mdio_freq = (100 * 1000 * 1000);
} else {
printf("%s: mdio=%d Hz\n", __func__, u_ar71xx_refclk);
u_ar71xx_mdio_freq = u_ar71xx_refclk;
}
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
}
static void
ar934x_chip_device_stop(uint32_t mask)
{
uint32_t reg;
reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg | mask);
}
static void
ar934x_chip_device_start(uint32_t mask)
{
uint32_t reg;
reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
ATH_WRITE_REG(AR934X_RESET_REG_RESET_MODULE, reg & ~mask);
}
static int
ar934x_chip_device_stopped(uint32_t mask)
{
uint32_t reg;
reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE);
return ((reg & mask) == mask);
}
static void
ar934x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
{
/* XXX TODO */
return;
}
/*
* XXX TODO !!
*/
static void
ar934x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
{
switch (unit) {
case 0:
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
ATH_WRITE_REG(AR934X_PLL_ETH_XMII_CONTROL_REG, pll);
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
break;
case 1:
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
/* XXX nothing */
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
break;
default:
printf("%s: invalid PLL set for arge unit: %d\n",
__func__, unit);
return;
}
}
static void
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
ar934x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
{
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
switch (id) {
case AR71XX_CPU_DDR_FLUSH_GE0:
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
break;
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
case AR71XX_CPU_DDR_FLUSH_GE1:
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
break;
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
case AR71XX_CPU_DDR_FLUSH_USB:
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_USB);
break;
case AR71XX_CPU_DDR_FLUSH_PCIE:
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE);
break;
case AR71XX_CPU_DDR_FLUSH_WMAC:
ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_WMAC);
break;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
default:
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
printf("%s: invalid DDR flush id (%d)\n", __func__, id);
break;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
}
}
static uint32_t
ar934x_chip_get_eth_pll(unsigned int mac, int speed)
{
uint32_t pll;
switch (speed) {
case 10:
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
pll = AR934X_PLL_VAL_10;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
break;
case 100:
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
pll = AR934X_PLL_VAL_100;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
break;
case 1000:
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
pll = AR934X_PLL_VAL_1000;
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
break;
default:
printf("%s%d: invalid speed %d\n", __func__, mac, speed);
pll = 0;
}
return (pll);
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
}
static void
ar934x_chip_reset_ethernet_switch(void)
{
ar71xx_device_stop(AR934X_RESET_ETH_SWITCH);
DELAY(100);
ar71xx_device_start(AR934X_RESET_ETH_SWITCH);
DELAY(100);
[ar934x] do an ethernet analog reset; apparently some boards don't. Tested: * on IOData WN-G300R. may be same as Sitecom WLR-2100. Submitted by: Hiroki Mori <yamori813@yahoo.co.jp> Differential Revision: https://reviews.freebsd.org/D10621
2017-05-06 06:09:50 +00:00
ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
DELAY(100);
ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
DELAY(100);
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
}
static void
ar934x_configure_gmac(uint32_t gmac_cfg)
{
uint32_t reg;
reg = ATH_READ_REG(AR934X_GMAC_REG_ETH_CFG);
printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
reg &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
reg |= gmac_cfg;
ATH_WRITE_REG(AR934X_GMAC_REG_ETH_CFG, reg);
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
}
static void
ar934x_chip_init_usb_peripheral(void)
{
uint32_t reg;
reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP);
if (reg & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
return;
ar71xx_device_stop(AR934X_RESET_USBSUS_OVERRIDE);
DELAY(100);
ar71xx_device_start(AR934X_RESET_USB_PHY);
DELAY(100);
ar71xx_device_start(AR934X_RESET_USB_PHY_ANALOG);
DELAY(100);
ar71xx_device_start(AR934X_RESET_USB_HOST);
DELAY(100);
}
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
static void
ar934x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
{
/*
* XXX !
*
* Nothing to see here; although gmac0 can have its
* MII configuration changed, the register values
* are slightly different.
*/
}
/*
* XXX TODO: fetch default MII divider configuration
*/
static void
ar934x_chip_reset_wmac(void)
{
Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
2014-03-18 12:19:39 +00:00
/* XXX TODO */
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
}
static void
ar934x_chip_init_gmac(void)
{
long gmac_cfg;
if (resource_long_value("ar934x_gmac", 0, "gmac_cfg",
&gmac_cfg) == 0) {
printf("%s: gmac_cfg=0x%08lx\n",
__func__,
(long) gmac_cfg);
ar934x_configure_gmac((uint32_t) gmac_cfg);
}
}
Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
2014-03-18 12:19:39 +00:00
/*
* Reset the NAND Flash Controller.
*
* + active=1 means "make it active".
* + active=0 means "make it inactive".
*/
static void
ar934x_chip_reset_nfc(int active)
{
if (active) {
ar71xx_device_start(AR934X_RESET_NANDF);
DELAY(100);
ar71xx_device_start(AR934X_RESET_ETH_SWITCH_ANALOG);
DELAY(250);
} else {
ar71xx_device_stop(AR934X_RESET_ETH_SWITCH_ANALOG);
DELAY(250);
ar71xx_device_stop(AR934X_RESET_NANDF);
DELAY(100);
}
}
Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT
2015-01-03 06:55:58 +00:00
/*
* Configure the GPIO output mux setup.
*
* The AR934x introduced an output mux which allowed
* certain functions to be configured on any pin.
* Specifically, the switch PHY link LEDs and
* WMAC external RX LNA switches are not limited to
* a specific GPIO pin.
*/
static void
ar934x_chip_gpio_output_configure(int gpio, uint8_t func)
{
uint32_t reg, s;
uint32_t t;
if (gpio > AR934X_GPIO_COUNT)
return;
sys: Make use of our rounddown() macro when sys/param.h is available. No functional change.
2016-04-30 14:41:18 +00:00
reg = AR934X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT
2015-01-03 06:55:58 +00:00
s = 8 * (gpio % 4);
/* read-modify-write */
t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
t &= ~(0xff << s);
t |= func << s;
ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
/* flush write */
ATH_READ_REG(AR71XX_GPIO_BASE + reg);
}
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
struct ar71xx_cpu_def ar934x_chip_def = {
&ar934x_chip_detect_mem_size,
&ar934x_chip_detect_sys_frequency,
&ar934x_chip_device_stop,
&ar934x_chip_device_start,
&ar934x_chip_device_stopped,
&ar934x_chip_set_pll_ge,
&ar934x_chip_set_mii_speed,
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
&ar934x_chip_set_mii_if,
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
&ar934x_chip_get_eth_pll,
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
&ar934x_chip_ddr_flush,
Update the AR934x SoC support. * Add the MDIO clock probe during clock initialisation; * Update the ethernet PLL configuration function to use the correct values; * Add a GMAC block configuration to pull the configuration out of hints; * Add an ethernet switch reconfiguration method. Tested: * AR9344 SoC (DB120) .. however, this has been tested with extra patches in my tree (to fix the ethernet/MDIO support, SPI support, ethernet switch support) and thus it isn't enough to bring the full board support up.
2013-10-15 03:28:32 +00:00
&ar934x_chip_init_usb_peripheral,
&ar934x_chip_reset_ethernet_switch,
&ar934x_chip_reset_wmac,
&ar934x_chip_init_gmac,
Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
2014-03-18 12:19:39 +00:00
&ar934x_chip_reset_nfc,
Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT
2015-01-03 06:55:58 +00:00
&ar934x_chip_gpio_output_configure,
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
};
Reference in New Issue Copy Permalink