75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
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/*-
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* Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TI_WDT_H_
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#define _TI_WDT_H_
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/* TI WDT registers */
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#define TI_WDT_WIDR 0x00 /* Watchdog Identification Register */
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#define TI_WDT_WDSC 0x10 /* Watchdog System Control Register */
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#define TI_WDT_WDST 0x14 /* Watchdog Status Register */
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#define TI_WDT_WISR 0x18 /* Watchdog Interrupt Status Register */
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#define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */
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#define TI_WDT_WCLR 0x24 /* Watchdog Control Register */
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#define TI_WDT_WCRR 0x28 /* Watchdog Counter Register */
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#define TI_WDT_WLDR 0x2c /* Watchdog Load Register */
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#define TI_WDT_WTGR 0x30 /* Watchdog Trigger Register */
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#define TI_WDT_WWPS 0x34 /* Watchdog Write Posting Register */
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#define TI_WDT_WDLY 0x44 /* Watchdog Delay Configuration Reg */
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#define TI_WDT_WSPR 0x48 /* Watchdog Start/Stop Register */
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#define TI_WDT_WIRQSTATRAW 0x54 /* Watchdog Raw Interrupt Status Reg. */
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#define TI_WDT_WIRQSTAT 0x58 /* Watchdog Int. Status Register */
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#define TI_WDT_WIRQENSET 0x5c /* Watchdog Int. Enable Set Register */
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#define TI_WDT_WIRQENCLR 0x60 /* Watchdog Int. Enable Clear Reg. */
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/* WDT_WDSC Register */
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#define TI_WDSC_SR (1 << 1) /* Soft reset */
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/*
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* WDT_WWPS Register
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*
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* Writes to some registers require synchronisation with a different clock
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* domain. The WDT_WWPS register is the place where this synchronisation
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* happens.
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*/
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#define TI_W_PEND_WCLR (1 << 0)
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#define TI_W_PEND_WCRR (1 << 1)
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#define TI_W_PEND_WLDR (1 << 2)
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#define TI_W_PEND_WTGR (1 << 3)
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#define TI_W_PEND_WSPR (1 << 4)
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#define TI_W_PEND_WDLY (1 << 5)
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/* WDT_WIRQENSET Register */
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#define TI_IRQ_EN_OVF (1 << 0) /* Overflow interrupt */
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#define TI_IRQ_EN_DLY (1 << 1) /* Delay interrupt */
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/* WDT_WIRQSTAT Register */
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#define TI_IRQ_EV_OVF (1 << 0) /* Overflow event */
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#define TI_IRQ_EV_DLY (1 << 1) /* Delay event */
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#endif /* _TI_WDT_H_ */
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