2004-05-14 11:46:45 +00:00
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/* $NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _ARM_SA11X0_REG_H_
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#define _ARM_SA11X0_REG_H_
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/* Physical register base addresses */
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#define SAOST_BASE 0x90000000 /* OS Timer */
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#define SARTC_BASE 0x90010000 /* Real-Time Clock */
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#define SAPMR_BASE 0x90020000 /* Power Manager */
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#define SARCR_BASE 0x90030000 /* Reset Controller */
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#define SAGPIO_BASE 0x90040000 /* GPIO */
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#define SAIPIC_BASE 0x90050000 /* Interrupt Controller */
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2006-05-23 12:14:14 +00:00
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#define SAIPIC_SIZE 0x24
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2004-05-14 11:46:45 +00:00
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#define SAPPC_BASE 0x90060000 /* Peripheral Pin Controller */
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#define SAUDC_BASE 0x80000000 /* USB Device Controller*/
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#define SACOM1_BASE 0x80010000 /* GPCLK/UART 1 */
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2006-05-23 12:14:14 +00:00
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#define SACOM1_SIZE 0x24
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2004-05-14 11:46:45 +00:00
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#define SACOM3_HW_BASE 0x80050000 /* UART 3 */
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#define SAMCP_BASE 0x80060000 /* MCP Controller */
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#define SASSP_BASE 0x80070000 /* Synchronous serial port */
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#define SADMAC_BASE 0xB0000000 /* DMA Controller */
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#define SALCD_BASE 0xB0100000 /* LCD */
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/* Register base virtual addresses mapped by initarm() */
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2006-05-22 23:25:34 +00:00
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#define SACOM1_VBASE 0xd000d000
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2004-05-14 11:46:45 +00:00
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/* Interrupt controller registers */
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#define SAIPIC_NPORTS 9
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#define SAIPIC_IP 0x00 /* IRQ pending register */
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#define SAIPIC_MR 0x04 /* Mask register */
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#define SAIPIC_LR 0x08 /* Level register */
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#define SAIPIC_FP 0x10 /* FIQ pending register */
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#define SAIPIC_PR 0x20 /* Pending register */
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#define SAIPIC_CR 0x0C /* Control register */
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/* width of interrupt controller */
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#define ICU_LEN 32
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/* Reset controller registers */
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#define SARCR_RSRR 0x0 /* Software reset register */
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#define SARCR_RCSR 0x4 /* Reset status register */
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#define SARCR_TUCR 0x8 /* Test Unit control reg */
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#endif /* _ARM_SA11X0_REG_H_ */
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