2010-10-06 22:25:21 +00:00
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/*-
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* Copyright (c) 2005 Gallon Sylvestre. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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2012-06-13 04:52:19 +00:00
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/*
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2010-10-06 22:25:21 +00:00
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* $FreeBSD$
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*/
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#ifndef ARM_AT91_AT91WDTREG_H
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#define ARM_AT91_AT91WDTREG_H
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#ifndef WDT_CLOCK
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#define WDT_CLOCK (32768)
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#endif
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#define WDT_DIV (128) /* Clock is slow clock / 128 */
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#define WDT_CR 0x0 /* Control Register */
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#define WDT_MR 0x4 /* Mode Register */
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#define WDT_SR 0x8 /* Status Register */
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/* WDT_CR */
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#define WDT_KEY (0xa5<<24)
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#define WDT_WDRSTT 0x1
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/* WDT_MR */
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#define WDT_WDV(x) (x & 0xfff) /* counter value*/
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#define WDT_WDFIEN (1<<12) /* enable interrupt */
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#define WDT_WDRSTEN (1<<13) /* enable reset */
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#define WDT_WDRPROC (1<<14) /* processor reset */
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#define WDT_WDDIS (1<<15) /* disable */
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#define WDT_WDD(x) ((x & 0xfff) << 16) /* delta value */
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#define WDT_WDDBGHLT (1<<28) /* halt in debug */
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#define WDT_WDIDLEHLT (1<<29) /* halt in idle */
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/* WDT_SR */
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#define WDT_WDUNF 0x1
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#define WDT_WDERR 0x2
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#endif /* ARM_AT91_AT91WDTREG_H */
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