50 lines
2.0 KiB
C
50 lines
2.0 KiB
C
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/*-
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* Copyright (C) 2008 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_VIAREG_H_
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#define _POWERPC_VIAREG_H_
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/* VIA interface registers */
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#define vBufB 0x0000 /* register B */
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#define vBufA 0x0200 /* register A */
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#define vDirB 0x0400 /* data direction register */
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#define vDirA 0x0600 /* data direction register */
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#define vSR 0x1400 /* shift register */
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#define vACR 0x1600 /* aux control register */
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#define vPCR 0x1800 /* peripheral control register */
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#define vIFR 0x1a00 /* interrupt flag register */
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#define vIER 0x1c00 /* interrupt enable register */
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#define vPB 0x0000
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#define vPB3 0x08
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#define vPB4 0x10
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#define vPB5 0x20
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#define vSR_INT 0x04
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#define vSR_OUT 0x10
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#endif /* _POWERPC_VIAREG_H_ */
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