58 lines
2.5 KiB
C
58 lines
2.5 KiB
C
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/*-
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* Copyright (c) 2005 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91STREG_H
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#define ARM_AT91_AT91STREG_H
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#define ST_CR 0x00 /* Control register */
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#define ST_PIMR 0x04 /* Period interval mode register */
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#define ST_WDMR 0x08 /* Watchdog mode register */
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#define ST_RTMR 0x0c /* Real-time mode register */
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#define ST_SR 0x10 /* Status register */
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#define ST_IER 0x14 /* Interrupt enable register */
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#define ST_IDR 0x18 /* Interrupt disable register */
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#define ST_IMR 0x1c /* Interrupt mask register */
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#define ST_RTAR 0x20 /* Real-time alarm register */
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#define ST_CRTR 0x24 /* Current real-time register */
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/* ST_CR */
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#define ST_CR_WDRST (1U << 0) /* WDRST: Watchdog Timer Restart */
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/* ST_WDMR */
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#define ST_WDMR_EXTEN (1U << 17) /* EXTEN: External Signal Assert Enable */
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#define ST_WDMR_RSTEN (1U << 16) /* RSTEN: Reset Enable */
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/* ST_SR, ST_IER, ST_IDR, ST_IMR */
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#define ST_SR_PITS (1U << 0) /* PITS: Period Interval Timer Status */
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#define ST_SR_WDOVF (1U << 1) /* WDOVF: Watchdog Overflow */
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#define ST_SR_RTTINC (1U << 2) /* RTTINC: Real-time Timer Increment */
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#define ST_SR_ALMS (1U << 3) /* ALMS: Alarm Status */
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/* ST_CRTR */
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#define ST_CRTR_MASK 0xfffff /* 20-bit counter */
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#endif /* ARM_AT91_AT91STREG_H */
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