454 lines
12 KiB
C
454 lines
12 KiB
C
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/*-
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* Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Allwinner A10/A20 DMA controller
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/allwinner/a10_dmac.h>
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#include <arm/allwinner/a10_clk.h>
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#include "sunxi_dma_if.h"
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#define NDMA_CHANNELS 8
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#define DDMA_CHANNELS 8
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enum a10dmac_type {
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CH_NDMA,
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CH_DDMA
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};
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struct a10dmac_softc;
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struct a10dmac_channel {
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struct a10dmac_softc * ch_sc;
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uint8_t ch_index;
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enum a10dmac_type ch_type;
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void (*ch_callback)(void *);
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void * ch_callbackarg;
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uint32_t ch_regoff;
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};
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struct a10dmac_softc {
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struct resource * sc_res[2];
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struct mtx sc_mtx;
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void * sc_ih;
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struct a10dmac_channel sc_ndma_channels[NDMA_CHANNELS];
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struct a10dmac_channel sc_ddma_channels[DDMA_CHANNELS];
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};
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static struct resource_spec a10dmac_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define DMA_READ(sc, reg) bus_read_4((sc)->sc_res[0], (reg))
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#define DMA_WRITE(sc, reg, val) bus_write_4((sc)->sc_res[0], (reg), (val))
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#define DMACH_READ(ch, reg) \
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DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff)
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#define DMACH_WRITE(ch, reg, val) \
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DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))
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static void a10dmac_intr(void *);
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static int
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a10dmac_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-dma"))
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return (ENXIO);
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device_set_desc(dev, "Allwinner DMA controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10dmac_attach(device_t dev)
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{
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struct a10dmac_softc *sc;
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unsigned int index;
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int error;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, a10dmac_spec, sc->sc_res)) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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mtx_init(&sc->sc_mtx, "a10 dmac", NULL, MTX_SPIN);
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/* Activate DMA controller clock */
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a10_clk_dmac_activate();
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/* Disable all interrupts and clear pending status */
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DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
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DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);
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/* Initialize channels */
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for (index = 0; index < NDMA_CHANNELS; index++) {
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sc->sc_ndma_channels[index].ch_sc = sc;
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sc->sc_ndma_channels[index].ch_index = index;
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sc->sc_ndma_channels[index].ch_type = CH_NDMA;
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sc->sc_ndma_channels[index].ch_callback = NULL;
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sc->sc_ndma_channels[index].ch_callbackarg = NULL;
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sc->sc_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index);
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DMACH_WRITE(&sc->sc_ndma_channels[index], AWIN_NDMA_CTL_REG, 0);
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}
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for (index = 0; index < DDMA_CHANNELS; index++) {
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sc->sc_ddma_channels[index].ch_sc = sc;
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sc->sc_ddma_channels[index].ch_index = index;
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sc->sc_ddma_channels[index].ch_type = CH_DDMA;
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sc->sc_ddma_channels[index].ch_callback = NULL;
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sc->sc_ddma_channels[index].ch_callbackarg = NULL;
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sc->sc_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index);
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DMACH_WRITE(&sc->sc_ddma_channels[index], AWIN_DDMA_CTL_REG, 0);
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}
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error = bus_setup_intr(dev, sc->sc_res[1], INTR_MPSAFE | INTR_TYPE_MISC,
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NULL, a10dmac_intr, sc, &sc->sc_ih);
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if (error != 0) {
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device_printf(dev, "could not setup interrupt handler\n");
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bus_release_resources(dev, a10dmac_spec, sc->sc_res);
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mtx_destroy(&sc->sc_mtx);
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return (ENXIO);
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}
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return (0);
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}
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static void
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a10dmac_intr(void *priv)
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{
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struct a10dmac_softc *sc = priv;
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uint32_t sta, bit, mask;
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uint8_t index;
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sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG);
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DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
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while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) {
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mask = (1U << (bit - 1));
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sta &= ~mask;
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/*
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* Map status bit to channel number. The status register is
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* encoded with two bits of status per channel (lowest bit
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* is half transfer pending, highest bit is end transfer
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* pending). The 8 normal DMA channel status are in the lower
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* 16 bits and the 8 dedicated DMA channel status are in
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* the upper 16 bits. The output is a channel number from 0-7.
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*/
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index = ((bit - 1) / 2) & 7;
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if (mask & AWIN_DMA_IRQ_NDMA) {
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if (sc->sc_ndma_channels[index].ch_callback == NULL)
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continue;
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sc->sc_ndma_channels[index].ch_callback(
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sc->sc_ndma_channels[index].ch_callbackarg);
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} else {
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if (sc->sc_ddma_channels[index].ch_callback == NULL)
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continue;
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sc->sc_ddma_channels[index].ch_callback(
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sc->sc_ddma_channels[index].ch_callbackarg);
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}
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}
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}
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static uint32_t
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a10dmac_read_ctl(struct a10dmac_channel *ch)
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{
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if (ch->ch_type == CH_NDMA) {
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return (DMACH_READ(ch, AWIN_NDMA_CTL_REG));
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} else {
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return (DMACH_READ(ch, AWIN_DDMA_CTL_REG));
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}
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}
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static void
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a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val)
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{
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if (ch->ch_type == CH_NDMA) {
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DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
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} else {
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DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
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}
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}
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static int
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a10dmac_set_config(device_t dev, void *priv, const struct sunxi_dma_config *cfg)
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{
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struct a10dmac_channel *ch = priv;
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uint32_t val;
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unsigned int dst_dw, dst_bl, dst_bs, dst_wc;
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unsigned int src_dw, src_bl, src_bs, src_wc;
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switch (cfg->dst_width) {
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case 8:
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dst_dw = AWIN_DMA_CTL_DATA_WIDTH_8;
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break;
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case 16:
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dst_dw = AWIN_DMA_CTL_DATA_WIDTH_16;
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break;
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case 32:
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dst_dw = AWIN_DMA_CTL_DATA_WIDTH_32;
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break;
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default:
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return (EINVAL);
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}
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switch (cfg->dst_burst_len) {
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case 1:
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dst_bl = AWIN_DMA_CTL_BURST_LEN_1;
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break;
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case 4:
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dst_bl = AWIN_DMA_CTL_BURST_LEN_4;
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break;
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case 8:
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dst_bl = AWIN_DMA_CTL_BURST_LEN_8;
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break;
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default:
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return (EINVAL);
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}
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switch (cfg->src_width) {
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case 8:
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src_dw = AWIN_DMA_CTL_DATA_WIDTH_8;
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break;
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case 16:
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src_dw = AWIN_DMA_CTL_DATA_WIDTH_16;
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break;
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case 32:
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src_dw = AWIN_DMA_CTL_DATA_WIDTH_32;
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break;
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default:
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return (EINVAL);
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}
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switch (cfg->src_burst_len) {
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case 1:
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src_bl = AWIN_DMA_CTL_BURST_LEN_1;
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break;
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case 4:
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src_bl = AWIN_DMA_CTL_BURST_LEN_4;
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break;
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case 8:
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src_bl = AWIN_DMA_CTL_BURST_LEN_8;
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break;
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default:
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return (EINVAL);
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}
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val = (dst_dw << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT) |
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(dst_bl << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT) |
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(cfg->dst_drqtype << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT) |
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(src_dw << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT) |
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(src_bl << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT) |
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(cfg->src_drqtype << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT);
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if (cfg->dst_noincr) {
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val |= AWIN_NDMA_CTL_DST_ADDR_NOINCR;
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}
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if (cfg->src_noincr) {
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val |= AWIN_NDMA_CTL_SRC_ADDR_NOINCR;
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}
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if (ch->ch_type == CH_NDMA) {
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DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
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} else {
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DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
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dst_bs = cfg->dst_blksize - 1;
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dst_wc = cfg->dst_wait_cyc - 1;
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src_bs = cfg->src_blksize - 1;
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src_wc = cfg->src_wait_cyc - 1;
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DMACH_WRITE(ch, AWIN_DDMA_PARA_REG,
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(dst_bs << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT) |
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(dst_wc << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT) |
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(src_bs << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT) |
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(src_wc << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT));
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}
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return (0);
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}
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static void *
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a10dmac_alloc(device_t dev, bool dedicated, void (*cb)(void *), void *cbarg)
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{
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struct a10dmac_softc *sc = device_get_softc(dev);
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struct a10dmac_channel *ch_list;
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struct a10dmac_channel *ch = NULL;
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uint32_t irqen;
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uint8_t ch_count, index;
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if (dedicated) {
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ch_list = sc->sc_ddma_channels;
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ch_count = DDMA_CHANNELS;
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} else {
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ch_list = sc->sc_ndma_channels;
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ch_count = NDMA_CHANNELS;
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}
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mtx_lock_spin(&sc->sc_mtx);
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for (index = 0; index < ch_count; index++) {
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if (ch_list[index].ch_callback == NULL) {
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ch = &ch_list[index];
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ch->ch_callback = cb;
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ch->ch_callbackarg = cbarg;
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irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
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if (ch->ch_type == CH_NDMA)
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irqen |= AWIN_DMA_IRQ_NDMA_END(index);
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else
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irqen |= AWIN_DMA_IRQ_DDMA_END(index);
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DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
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break;
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}
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}
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mtx_unlock_spin(&sc->sc_mtx);
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return (ch);
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}
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static void
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a10dmac_free(device_t dev, void *priv)
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{
|
||
|
|
struct a10dmac_channel *ch = priv;
|
||
|
|
struct a10dmac_softc *sc = ch->ch_sc;
|
||
|
|
uint32_t irqen, sta, cfg;
|
||
|
|
|
||
|
|
mtx_lock_spin(&sc->sc_mtx);
|
||
|
|
|
||
|
|
irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
|
||
|
|
cfg = a10dmac_read_ctl(ch);
|
||
|
|
if (ch->ch_type == CH_NDMA) {
|
||
|
|
sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index);
|
||
|
|
cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
|
||
|
|
} else {
|
||
|
|
sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index);
|
||
|
|
cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
|
||
|
|
}
|
||
|
|
irqen &= ~sta;
|
||
|
|
a10dmac_write_ctl(ch, cfg);
|
||
|
|
DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
|
||
|
|
DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
|
||
|
|
|
||
|
|
ch->ch_callback = NULL;
|
||
|
|
ch->ch_callbackarg = NULL;
|
||
|
|
|
||
|
|
mtx_unlock_spin(&sc->sc_mtx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
a10dmac_transfer(device_t dev, void *priv, bus_addr_t src, bus_addr_t dst,
|
||
|
|
size_t nbytes)
|
||
|
|
{
|
||
|
|
struct a10dmac_channel *ch = priv;
|
||
|
|
uint32_t cfg;
|
||
|
|
|
||
|
|
cfg = a10dmac_read_ctl(ch);
|
||
|
|
if (ch->ch_type == CH_NDMA) {
|
||
|
|
if (cfg & AWIN_NDMA_CTL_DMA_LOADING)
|
||
|
|
return (EBUSY);
|
||
|
|
|
||
|
|
DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src);
|
||
|
|
DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst);
|
||
|
|
DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes);
|
||
|
|
|
||
|
|
cfg |= AWIN_NDMA_CTL_DMA_LOADING;
|
||
|
|
a10dmac_write_ctl(ch, cfg);
|
||
|
|
} else {
|
||
|
|
if (cfg & AWIN_DDMA_CTL_DMA_LOADING)
|
||
|
|
return (EBUSY);
|
||
|
|
|
||
|
|
DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src);
|
||
|
|
DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst);
|
||
|
|
DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes);
|
||
|
|
|
||
|
|
cfg |= AWIN_DDMA_CTL_DMA_LOADING;
|
||
|
|
a10dmac_write_ctl(ch, cfg);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
a10dmac_halt(device_t dev, void *priv)
|
||
|
|
{
|
||
|
|
struct a10dmac_channel *ch = priv;
|
||
|
|
uint32_t cfg;
|
||
|
|
|
||
|
|
cfg = a10dmac_read_ctl(ch);
|
||
|
|
if (ch->ch_type == CH_NDMA) {
|
||
|
|
cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
|
||
|
|
} else {
|
||
|
|
cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
|
||
|
|
}
|
||
|
|
a10dmac_write_ctl(ch, cfg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static device_method_t a10dmac_methods[] = {
|
||
|
|
/* Device interface */
|
||
|
|
DEVMETHOD(device_probe, a10dmac_probe),
|
||
|
|
DEVMETHOD(device_attach, a10dmac_attach),
|
||
|
|
|
||
|
|
/* sunxi DMA interface */
|
||
|
|
DEVMETHOD(sunxi_dma_alloc, a10dmac_alloc),
|
||
|
|
DEVMETHOD(sunxi_dma_free, a10dmac_free),
|
||
|
|
DEVMETHOD(sunxi_dma_set_config, a10dmac_set_config),
|
||
|
|
DEVMETHOD(sunxi_dma_transfer, a10dmac_transfer),
|
||
|
|
DEVMETHOD(sunxi_dma_halt, a10dmac_halt),
|
||
|
|
|
||
|
|
DEVMETHOD_END
|
||
|
|
};
|
||
|
|
|
||
|
|
static driver_t a10dmac_driver = {
|
||
|
|
"a10dmac",
|
||
|
|
a10dmac_methods,
|
||
|
|
sizeof(struct a10dmac_softc)
|
||
|
|
};
|
||
|
|
|
||
|
|
static devclass_t a10dmac_devclass;
|
||
|
|
|
||
|
|
DRIVER_MODULE(a10dmac, simplebus, a10dmac_driver, a10dmac_devclass, 0, 0);
|