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freebsd-skq/sys/sparc64/include/dcr.h

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Flesh out MMU and cache handling of cheetah-class CPUs.
2008-09-04 19:58:52 +00:00
/*-
* Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_DCR_H_
#define _MACHINE_DCR_H_
/*
* Definitions for the UltraSPARC-III Depatch Control Register (ASR 18).
*/
#define DCR_MS (1UL << 0)
#define DCR_IFPOE (1UL << 1)
#define DCR_SI (1UL << 3)
#define DCR_RPE (1UL << 4)
#define DCR_BPE (1UL << 5)
#define DCR_OBSDATA_SHIFT 6
#define DCR_OBSDATA_CT_BITS 8
#define DCR_OBSDATA_CT_MASK \
(((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
Correct the DCR_IPE macro to refer to the right bit. Also improve the associated comment as besides US-IV+ these bits are only available with US-III++, i.e. the 1.2GHz version of the US-III+.
2010-04-10 11:13:51 +00:00
/* The following bits are valid for the UltraSPARC-III++/IV+ only. */
#define DCR_IPE (1UL << 2)
Flesh out MMU and cache handling of cheetah-class CPUs.
2008-09-04 19:58:52 +00:00
#define DCR_OBSDATA_CTP_BITS 6
#define DCR_OBSDATA_CTP_MASK \
(((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT)
#define DCR_DPE (1UL << 12)
/* The following bits are valid for the UltraSPARC-IV+ only. */
#define DCR_BPM_SHIFT 13
#define DCR_BPM_BITS 2
#define DCR_BPM_MASK \
(((1UL << DCR_BPM_BITS) - 1) << DCR_BPM_SHIFT)
o Add support for UltraSparc-IV+: - Swap the configuration of the first and second large dTLB as with US-IV+ these can only hold entries of certain page sizes each, which we happened to chose the non-working way around. - Additionally ensure that the large iTLB is set up to hold 8k pages (currently this happens to be a NOP though). - Add a workaround for US-IV+ erratum #2. - Turn off dTLB parity error reporting as otherwise we get seemingly false positives when copying in the user window by simulating a fill trap on return to usermode. Given that these parity errors can be avoided by disabling multi issue mode and the problem could be reproduced with a second machine this appears to be a silicon bug of some sort. - Add a membar #Sync also before the stores to ASI_DCACHE_TAG. While at it, turn of interrupts across the whole cheetah_cache_flush() for simplicity instead of around every flush. This should have next to no impact as for cheetah-class machines we typically only need to flush the caches a few times during boot when recovering from peeking/poking non-existent PCI devices, if at all. - Just use KERNBASE for FLUSH as we also do elsewhere as the US-IV+ documentation doesn't seem to mention that these CPUs also ignore the address like previous cheetah-class CPUs do. Again the code changing LSU_IC is executed seldom enough that the negligible optimization of using %g0 instead should have no real impact. With these changes FreeBSD runs stable on V890 equipped with US-IV+ and -j128 buildworlds in a loop for days are no problem. Unfortunately, the performance isn't were it should be as a buildworld on a 4x1.5GHz US-IV+ V890 takes nearly 3h while on a V440 with (theoretically) less powerfull 4x1.5GHz US-IIIi it takes just over 1h. It's unclear whether this is related to the supposed silicon bug mentioned above or due to another issue. The documentation (which contains a sever bug in the description of the bits added to the context registers though) at least doesn't mention any requirements for changes in the CPU handling besides those implemented and the cache as well as the TLB configurations and handling look fine. o Re-arrange cheetah_init() so it's easier to add support for SPARC64 V up to VIIIfx CPUs, which only require parts of this initialization.
2010-03-17 22:45:09 +00:00
#define DCR_BPM_1HIST_GSHARE (0UL << DCR_BPM_SHIFT)
#define DCR_BPM_2HIST_GSHARE (1UL << DCR_BPM_SHIFT)
#define DCR_BPM_PC (2UL << DCR_BPM_SHIFT)
#define DCR_BPM_2HIST_MIXED (3UL << DCR_BPM_SHIFT)
Flesh out MMU and cache handling of cheetah-class CPUs.
2008-09-04 19:58:52 +00:00
#define DCR_JPE (1UL << 15)
#define DCR_ITPE (1UL << 16)
#define DCR_DTPE (1UL << 17)
#define DCR_PPE (1UL << 18)
#endif /* _MACHINE_DCR_H_ */
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