109 lines
3.8 KiB
C
109 lines
3.8 KiB
C
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/*-
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* Copyright (c) 2008, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_JMPHYREG_H_
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#define _DEV_MII_JMPHYREG_H_
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/*
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* Registers for the JMicron JMC250 Gigabit PHY.
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*/
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/* PHY specific status register. */
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#define JMPHY_SSR 0x11
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#define JMPHY_SSR_SPEED_1000 0x8000
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#define JMPHY_SSR_SPEED_100 0x4000
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#define JMPHY_SSR_SPEED_10 0x0000
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#define JMPHY_SSR_SPEED_MASK 0xC000
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#define JMPHY_SSR_DUPLEX 0x2000
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#define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800
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#define JMPHY_SSR_LINK_UP 0x0400
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#define JMPHY_SSR_MDI_XOVER 0x0040
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#define JMPHY_SSR_INV_POLARITY 0x0002
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/* PHY specific cable length status register. */
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#define JMPHY_SCL 0x17
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#define JMPHY_SCL_CHAN_D_MASK 0xF000
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#define JMPHY_SCL_CHAN_C_MASK 0x0F00
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#define JMPHY_SCL_CHAN_B_MASK 0x00F0
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#define JMPHY_SCL_CHAN_A_MASK 0x000F
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#define JMPHY_SCL_LEN_35 0
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#define JMPHY_SCL_LEN_40 1
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#define JMPHY_SCL_LEN_50 2
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#define JMPHY_SCL_LEN_60 3
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#define JMPHY_SCL_LEN_70 4
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#define JMPHY_SCL_LEN_80 5
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#define JMPHY_SCL_LEN_90 6
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#define JMPHY_SCL_LEN_100 7
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#define JMPHY_SCL_LEN_110 8
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#define JMPHY_SCL_LEN_120 9
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#define JMPHY_SCL_LEN_130 10
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#define JMPHY_SCL_LEN_140 11
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#define JMPHY_SCL_LEN_150 12
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#define JMPHY_SCL_LEN_160 13
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#define JMPHY_SCL_LEN_170 14
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#define JMPHY_SCL_RSVD 15
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/* PHY specific LED control register 1. */
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#define JMPHY_LED_CTL1 0x18
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#define JMPHY_LED_BLINK_42MS 0x0000
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#define JMPHY_LED_BLINK_84MS 0x2000
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#define JMPHY_LED_BLINK_170MS 0x4000
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#define JMPHY_LED_BLINK_340MS 0x6000
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#define JMPHY_LED_BLINK_670MS 0x8000
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#define JMPHY_LED_BLINK_MASK 0xE000
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#define JMPHY_LED_FLP_GAP_MASK 0x1F00
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#define JMPHY_LED_FLP_GAP_DEFULT 0x1000
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#define JMPHY_LED2_POLARITY_MASK 0x0030
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#define JMPHY_LED1_POLARITY_MASK 0x000C
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#define JMPHY_LED0_POLARITY_MASK 0x0003
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#define JMPHY_LED_ON_LO_OFF_HI 0
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#define JMPHY_LED_ON_HI_OFF_HI 1
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#define JMPHY_LED_ON_LO_OFF_TS 2
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#define JMPHY_LED_ON_HI_OFF_TS 3
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/* PHY specific LED control register 2. */
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#define JMPHY_LED_CTL2 0x19
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#define JMPHY_LED_NO_STRETCH 0x0000
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#define JMPHY_LED_STRETCH_42MS 0x2000
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#define JMPHY_LED_STRETCH_84MS 0x4000
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#define JMPHY_LED_STRETCH_170MS 0x6000
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#define JMPHY_LED_STRETCH_340MS 0x8000
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#define JMPHY_LED_STRETCH_670MS 0xB000
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#define JMPHY_LED_STRETCH_1300MS 0xC000
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#define JMPHY_LED_STRETCH_2700MS 0xE000
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#define JMPHY_LED2_MODE_MASK 0x0F00
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#define JMPHY_LED1_MODE_MASK 0x00F0
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#define JMPHY_LED0_MODE_MASK 0x000F
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/* PHY specific test mode control register. */
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#define JMPHY_TMCTL 0x1A
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#define JMPHY_TMCTL_SLEEP_ENB 0x1000
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#endif /* _DEV_MII_JMPHYREG_H_ */
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