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freebsd-skq/sys/mips/atheros/ar71xx_cpudef.h

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Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
/*-
* Copyright (c) 2010 Adrian Chadd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef __AR71XX_CPUDEF_H__
#define __AR71XX_CPUDEF_H__
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
typedef enum {
AR71XX_CPU_DDR_FLUSH_GE0,
AR71XX_CPU_DDR_FLUSH_GE1,
AR71XX_CPU_DDR_FLUSH_USB,
AR71XX_CPU_DDR_FLUSH_PCIE,
AR71XX_CPU_DDR_FLUSH_WMAC,
AR71XX_CPU_DDR_FLUSH_PCIE_EP,
AR71XX_CPU_DDR_FLUSH_CHECKSUM,
} ar71xx_flush_ddr_id_t;
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
struct ar71xx_cpu_def {
void (* detect_mem_size) (void);
void (* detect_sys_frequency) (void);
void (* ar71xx_chip_device_stop) (uint32_t);
void (* ar71xx_chip_device_start) (uint32_t);
int (* ar71xx_chip_device_stopped) (uint32_t);
Further ar71xx MII support improvements. * Flesh out the PLL configuration fetch function, which will return the PLL configuration based on the unit number and speed. * Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config function - pass in a 'pll' value instead. * Modify arge_set_pll() to: + fetch the PLL configuration + write the PLL configuration + update the MII speed configuration. This will allow if_arge to override the PLL configuration as required. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t);
Begin fleshing out MII clock rate configuration changes. These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined.
2012-03-17 07:25:23 +00:00
void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t);
MII related infrastructure changes. * Add a new method to set the MII mode - GMII, RGMII, RMII, MII. + arge0 supports all four (two for non-Gige interfaces.) + arge1 only supports two (one for non-gige interfaces.) * Set the MII clock speed when changing the MAC PLL speed. + Needed for AR91xx and AR71xx; not needed for AR724x. Tested: * AR71xx only, I'll do AR913x testing tonight and fix whichever issues creep up. TODO: * Implement the missing AR7242 arge0 PLL configuration, but don't adjust the MII speed accordingly. * .. the AR7240/AR7241 don't require this, so make sure it's not set accidentally. Bugs (not fixed here): * Statically configured arge speeds are still broken - investigate why that is on the AP96 board. Autonegotiate is working fine, but there still seems to be an occasionally heavy packet loss issue. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00
void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode);
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int);
/*
* From Linux - Handling this IRQ is a bit special.
* AR71xx - AR71XX_DDR_REG_FLUSH_PCI
* AR724x - AR724X_DDR_REG_FLUSH_PCIE
* AR91xx - AR91XX_DDR_REG_FLUSH_WMAC
*
* These are set when STATUSF_IP2 is set in regiser c0.
* This flush is done before the IRQ is handled to make
* sure the driver correctly sees any memory updates.
*/
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
void (* ar71xx_chip_ddr_flush) (ar71xx_flush_ddr_id_t id);
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
/*
* The USB peripheral init code is subtly different for
* each chip.
*/
void (* ar71xx_chip_init_usb_peripheral) (void);
Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane.
2013-10-15 01:35:48 +00:00
void (* ar71xx_chip_reset_ethernet_switch) (void);
void (* ar71xx_chip_reset_wmac) (void);
void (* ar71xx_chip_init_gmac) (void);
Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
2014-03-18 12:19:39 +00:00
void (* ar71xx_chip_reset_nfc) (int);
Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT
2015-01-03 06:55:58 +00:00
void (* ar71xx_chip_gpio_out_configure) (int, uint8_t);
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
};
extern struct ar71xx_cpu_def * ar71xx_cpu_ops;
static inline void ar71xx_detect_sys_frequency(void)
{
ar71xx_cpu_ops->detect_sys_frequency();
}
static inline void ar71xx_device_stop(uint32_t mask)
{
ar71xx_cpu_ops->ar71xx_chip_device_stop(mask);
}
static inline void ar71xx_device_start(uint32_t mask)
{
ar71xx_cpu_ops->ar71xx_chip_device_start(mask);
}
static inline int ar71xx_device_stopped(uint32_t mask)
{
return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask);
}
Further ar71xx MII support improvements. * Flesh out the PLL configuration fetch function, which will return the PLL configuration based on the unit number and speed. * Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config function - pass in a 'pll' value instead. * Modify arge_set_pll() to: + fetch the PLL configuration + write the PLL configuration + update the MII speed configuration. This will allow if_arge to override the PLL configuration as required. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll)
add the PLL set functions to cpuops
2010-08-19 16:15:30 +00:00
{
Further ar71xx MII support improvements. * Flesh out the PLL configuration fetch function, which will return the PLL configuration based on the unit number and speed. * Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config function - pass in a 'pll' value instead. * Modify arge_set_pll() to: + fetch the PLL configuration + write the PLL configuration + update the MII speed configuration. This will allow if_arge to override the PLL configuration as required. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll);
add the PLL set functions to cpuops
2010-08-19 16:15:30 +00:00
}
Begin fleshing out MII clock rate configuration changes. These are needed for some particular port configurations where the default speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit PLL rate requires a similar MII clock rate, rather than a fixed MII rate.) This is: * only currently implemented for the ar71xx; * isn't used anywhere (yet), as the final interface for this hasn't yet been determined.
2012-03-17 07:25:23 +00:00
static inline void ar71xx_device_set_mii_speed(int unit, int speed)
{
ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed);
}
MII related infrastructure changes. * Add a new method to set the MII mode - GMII, RGMII, RMII, MII. + arge0 supports all four (two for non-Gige interfaces.) + arge1 only supports two (one for non-gige interfaces.) * Set the MII clock speed when changing the MAC PLL speed. + Needed for AR91xx and AR71xx; not needed for AR724x. Tested: * AR71xx only, I'll do AR913x testing tonight and fix whichever issues creep up. TODO: * Implement the missing AR7242 arge0 PLL configuration, but don't adjust the MII speed accordingly. * .. the AR7240/AR7241 don't require this, so make sure it's not set accidentally. Bugs (not fixed here): * Statically configured arge speeds are still broken - investigate why that is on the AP96 board. Autonegotiate is working fine, but there still seems to be an occasionally heavy packet loss issue. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00
static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg)
{
ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg);
}
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
static inline void ar71xx_device_flush_ddr(ar71xx_flush_ddr_id_t id)
add the PLL set functions to cpuops
2010-08-19 16:15:30 +00:00
{
Reshuffle all of the DDR flush operations into a single switch/mux, and start teaching subsystems about it. The Atheros MIPS platforms don't guarantee any kind of FIFO consistency with interrupts in hardware. So software needs to do a flush when it receives an interrupt and before it calls the interrupt handler. There are new ones for the QCA934x and QCA955x, so do a few things: * Get rid of the individual ones (for ethernet and IP2); * Create a mux and enum listing all the variations on DDR flushes; * replace the uses of IP2 with the relevant one (which will typically be "PCI" here); * call the USB DDR flush before calling the real USB interrupt handlers; * call the ethernet one upon receiving an interrupt that's for us, rather than never calling it during operation. Tested: * QCA9558 (TP-Link archer c7 v2) * AR9331 (Carambola 2) TODO: * PCI, USB, ethernet, etc need to do a double-check to see if the interrupt was truely for them before doing the DDR. For now I prefer "correct" over "fast".
2015-07-04 03:05:57 +00:00
ar71xx_cpu_ops->ar71xx_chip_ddr_flush(id);
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
}
Further ar71xx MII support improvements. * Flesh out the PLL configuration fetch function, which will return the PLL configuration based on the unit number and speed. * Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config function - pass in a 'pll' value instead. * Modify arge_set_pll() to: + fetch the PLL configuration + write the PLL configuration + update the MII speed configuration. This will allow if_arge to override the PLL configuration as required. Obtained from: Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed)
{
return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed));
}
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
static inline void ar71xx_init_usb_peripheral(void)
{
ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral();
}
Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane.
2013-10-15 01:35:48 +00:00
static inline void ar71xx_reset_ethernet_switch(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch)
ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch();
}
static inline void ar71xx_reset_wmac(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac)
ar71xx_cpu_ops->ar71xx_chip_reset_wmac();
}
static inline void ar71xx_init_gmac(void)
{
if (ar71xx_cpu_ops->ar71xx_chip_init_gmac)
ar71xx_cpu_ops->ar71xx_chip_init_gmac();
}
Extend the Atheros SoC support to include a method to enable/disable the NAND flash controller. Add the AR934x NAND flash controller reset routines. (It's different on subsequent SoCs.) Tested: * AR9344, Atheros DB120 reference platform Obtained from: OpenWRT
2014-03-18 12:19:39 +00:00
static inline void ar71xx_reset_nfc(int active)
{
if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc)
ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active);
}
Add a GPIO output mux configuration method. The AR934x and later (which will turn up eventually) have a new GPIO output configuration option - a real MUX rather than a "GPIO or this function." For now I'm squirreling it away in the CPU code just so it's done - I may move this to the GPIO layer later. Specifically, this is required for setting up some boards that have external receive side LNA (low noise amplifier) that gets switched on/off by the on-chip wireless MAC. If we don't add this support for those boards then we'll end up with really poor performance. (I don't yet have one of those APs, but it'll likely show up in a week.) Obtained from: Linux OpenWRT
2015-01-03 06:55:58 +00:00
static inline void ar71xx_gpio_ouput_configure(int gpio, uint8_t func)
{
if (ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure)
ar71xx_cpu_ops->ar71xx_chip_gpio_out_configure(gpio, func);
}
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
/* XXX shouldn't be here! */
Add the reference clock for each supported chip. Obtained from: Linux (openwrt)
2013-03-27 03:33:19 +00:00
extern uint32_t u_ar71xx_refclk;
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
extern uint32_t u_ar71xx_cpu_freq;
extern uint32_t u_ar71xx_ahb_freq;
extern uint32_t u_ar71xx_ddr_freq;
Add two new CPU specific definitions - the watchdog clock frequency and the UART clock frequency. The AR933x and AR934x have separate PLL settings for these.
2013-07-21 03:51:24 +00:00
extern uint32_t u_ar71xx_uart_freq;
extern uint32_t u_ar71xx_wdt_freq;
Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane.
2013-10-15 01:35:48 +00:00
extern uint32_t u_ar71xx_mdio_freq;
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
Add the reference clock for each supported chip. Obtained from: Linux (openwrt)
2013-03-27 03:33:19 +00:00
static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; }
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; }
static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; }
static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; }
Add two new CPU specific definitions - the watchdog clock frequency and the UART clock frequency. The AR933x and AR934x have separate PLL settings for these.
2013-07-21 03:51:24 +00:00
static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; }
static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; }
Add new features - an MDIO clock, WMAC reset, GMAC reset and ethernet switch reset/initialise functions. The AR934x and QC955x SoCs both have a configurable MDIO base clock. The others have the MDIO clock use the same clock as the system reference clock, whatever that may be. Tested: * AR9344 SoC TODO: * mips24k - AR933x would be fine for now, just to ensure that things are sane.
2013-10-15 01:35:48 +00:00
static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; }
Add two new CPU specific definitions - the watchdog clock frequency and the UART clock frequency. The AR933x and AR934x have separate PLL settings for these.
2013-07-21 03:51:24 +00:00
Bring over the first cut of the Atheros-specific SoC operations. Each of these SoCs have different devices, different hardware initialisation methods and, quite likely, different quirks. These functions will abstract out the SoC differences and keep these differences out of the drivers (eg USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
#endif
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