2012-08-25 08:31:21 +00:00
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# $FreeBSD$
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MFP4: 221483, 221567, 221568, 221670, 221677, 221678, 221800, 221801,
221804, 221805, 222004, 222006, 222055, 222820, 1135077, 1135118, 1136259
Add atse(4), a driver for the Altera Triple Speed Ethernet MegaCore.
The current driver support gigabit Ethernet speeds only and works with
the MegaCore only in the internal FIFO configuration in the soon to be
open sourced BERI CPU configuration.
Submitted by: bz
MFC after: 3 days
Sponsored by: DARPA/AFRL
2013-10-18 20:44:19 +00:00
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dev/altera/atse/if_atse.c optional altera_atse
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dev/altera/atse/if_atse_fdt.c optional altera_atse fdt
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dev/altera/atse/if_atse_nexus.c optional altera_atse
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Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core,
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG. This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores. As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints. UART instances appear in /dev
as ttyu0, ttyu1, etc.
However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues. We work around
these as best we can, using various heuristics.
While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.
Sponsored by: DARPA, AFRL
2012-08-25 11:30:36 +00:00
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dev/altera/jtag_uart/altera_jtag_uart_cons.c optional altera_jtag_uart
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dev/altera/jtag_uart/altera_jtag_uart_tty.c optional altera_jtag_uart
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2013-01-13 15:08:17 +00:00
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dev/altera/jtag_uart/altera_jtag_uart_fdt.c optional altera_jtag_uart fdt
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Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core,
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG. This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores. As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints. UART instances appear in /dev
as ttyu0, ttyu1, etc.
However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues. We work around
these as best we can, using various heuristics.
While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.
Sponsored by: DARPA, AFRL
2012-08-25 11:30:36 +00:00
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dev/altera/jtag_uart/altera_jtag_uart_nexus.c optional altera_jtag_uart
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2012-08-26 09:21:59 +00:00
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dev/terasic/de4led/terasic_de4led.c optional terasic_de4led
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2013-01-13 15:12:35 +00:00
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dev/terasic/de4led/terasic_de4led_fdt.c optional terasic_de4led fdt
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2012-08-26 09:21:59 +00:00
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dev/terasic/de4led/terasic_de4led_nexus.c optional terasic_de4led
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Add terasic_mtl(4), a device driver for the Terasic Multi-Touch LCD,
used with Terasic's DE-4 and other similar FPGA boards. This display
is 800x480 and includes a capacitive touch screen, multi-touch
gesture recognition, etc. This device driver depends on a Cambridge-
provided IP core that allows the MTL device to be hooked up to the
Altera Avalon SoC bus, and also provides a VGA-like text frame buffer.
Although it is compiled as a single device driver, it actually
implements a number of different device nodes exporting various
aspects of this multi-function device to userspace:
- Simple memory-mapped driver for the MTL 24-bit pixel frame buffer.
- Simple memory-mapped driver for the MTL control register set.
- Simple memory-mapped driver for the MTL text frame buffer.
- syscons attachment for the MTL text frame buffer.
This driver attaches directly to Nexus as is common for SoC device
drivers, and for the time being is considered BERI-specific, although
in principle it might be used with other hard and soft cores on
Altera FPGAs.
Control registers, including touchscreen input, are simply memory
mapped; in the future it would be desirable to hook up a more
conventional device node that can stream events, support kqueue(2)/
poll(2)/select(2), etc.
This is the first use of syscons on MIPS, as far as I can tell, and
there are some loose ends, such as an inability to use the hardware
cursor. More fundamentally, it appears that syscons(4) assumes that
either a host is PC-like (i386, amd64) *or* it must be using a
graphical frame buffer. While the MTL supports a graphical frame
buffer, using the text frame buffer is preferable for console use.
Fixing this issue in syscons(4) requires non-trivial changes, as the
text frame buffer support assumes that direct memory access can be
done to the text frame buffer without using bus accessor methods,
which is not the case on MIPS. As a workaround for this, we instead
double-buffer and pretend to be a graphical frame buffer exposing
text accessor methods, leading to some quirks in syscons behaviour.
Sponsored by: DARPA, AFRL
2012-08-25 22:35:29 +00:00
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dev/terasic/mtl/terasic_mtl.c optional terasic_mtl
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2013-01-13 16:27:56 +00:00
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dev/terasic/mtl/terasic_mtl_fdt.c optional terasic_mtl fdt
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Add terasic_mtl(4), a device driver for the Terasic Multi-Touch LCD,
used with Terasic's DE-4 and other similar FPGA boards. This display
is 800x480 and includes a capacitive touch screen, multi-touch
gesture recognition, etc. This device driver depends on a Cambridge-
provided IP core that allows the MTL device to be hooked up to the
Altera Avalon SoC bus, and also provides a VGA-like text frame buffer.
Although it is compiled as a single device driver, it actually
implements a number of different device nodes exporting various
aspects of this multi-function device to userspace:
- Simple memory-mapped driver for the MTL 24-bit pixel frame buffer.
- Simple memory-mapped driver for the MTL control register set.
- Simple memory-mapped driver for the MTL text frame buffer.
- syscons attachment for the MTL text frame buffer.
This driver attaches directly to Nexus as is common for SoC device
drivers, and for the time being is considered BERI-specific, although
in principle it might be used with other hard and soft cores on
Altera FPGAs.
Control registers, including touchscreen input, are simply memory
mapped; in the future it would be desirable to hook up a more
conventional device node that can stream events, support kqueue(2)/
poll(2)/select(2), etc.
This is the first use of syscons on MIPS, as far as I can tell, and
there are some loose ends, such as an inability to use the hardware
cursor. More fundamentally, it appears that syscons(4) assumes that
either a host is PC-like (i386, amd64) *or* it must be using a
graphical frame buffer. While the MTL supports a graphical frame
buffer, using the text frame buffer is preferable for console use.
Fixing this issue in syscons(4) requires non-trivial changes, as the
text frame buffer support assumes that direct memory access can be
done to the text frame buffer without using bus accessor methods,
which is not the case on MIPS. As a workaround for this, we instead
double-buffer and pretend to be a graphical frame buffer exposing
text accessor methods, leading to some quirks in syscons behaviour.
Sponsored by: DARPA, AFRL
2012-08-25 22:35:29 +00:00
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dev/terasic/mtl/terasic_mtl_nexus.c optional terasic_mtl
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dev/terasic/mtl/terasic_mtl_pixel.c optional terasic_mtl
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dev/terasic/mtl/terasic_mtl_reg.c optional terasic_mtl
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dev/terasic/mtl/terasic_mtl_syscons.c optional terasic_mtl
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dev/terasic/mtl/terasic_mtl_text.c optional terasic_mtl
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2012-08-25 08:31:21 +00:00
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mips/beri/beri_machdep.c standard
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2013-10-22 15:29:59 +00:00
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mips/beri/beri_pic.c optional fdt
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2012-08-25 08:31:21 +00:00
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mips/mips/intr_machdep.c standard
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mips/mips/tick.c standard
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