d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove kernel support for armeb

Browse Source 
Remove all the big-endian arm architectures (ixp425 and ixp435)
support in the kernel and associated drivers.

Differential Revision:  https://reviews.freebsd.org/D16257
This commit is contained in:
imp 2018-07-17 23:23:45 +00:00
parent 1696abd6bd
commit 000ad38a32
59 changed files with 14 additions and 13308 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
sys/arm/arm/cpufunc.c
View File

@ -65,11 +65,6 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/i8134x/i81342reg.h>
#endif
#ifdef CPU_XSCALE_IXP425
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#endif
/* PRIMARY CACHE VARIABLES */
int arm_picache_size;
int arm_picache_line_size;
@ -259,7 +254,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
};
#endif /* CPU_MV_PJ4B */
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
#if defined(CPU_XSCALE_PXA2X0)
struct cpu_functions xscale_cpufuncs = {
/* CPU functions */
@ -309,7 +304,7 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */
};
#endif
/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
/* CPU_XSCALE_PXA2X0 */
#ifdef CPU_XSCALE_81342
struct cpu_functions xscalec3_cpufuncs = {
@ -467,7 +462,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore-v4.s */
#if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || \
defined(CPU_ARM1176) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_PXA2X0) || \
defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
defined(CPU_XSCALE_81342) || \
defined(CPU_CORTEXA) || defined(CPU_KRAIT)
@ -725,18 +720,6 @@ set_cpufuncs(void)
goto out;
}
#endif /* CPU_XSCALE_PXA2X0 */
#ifdef CPU_XSCALE_IXP425
if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 ||
cputype == CPU_ID_IXP425_266 || cputype == CPU_ID_IXP435) {
cpufuncs = xscale_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
goto out;
}
#endif /* CPU_XSCALE_IXP425 */
/*
* Bzzzz. And the answer was ...
*/
@ -950,8 +933,7 @@ fa526_setup(void)
}
#endif /* CPU_FA526 */
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342)
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
void
xscale_setup(void)
{
@ -1017,4 +999,4 @@ xscale_setup(void)
__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl));
}
#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#endif /* CPU_XSCALE_PXA2X0 */

2
sys/arm/arm/elf_trampoline.c
View File

@ -70,7 +70,7 @@ extern void fa526_idcache_wbinv_all(void);
#elif defined(CPU_ARM9E)
#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
extern void armv5_ec_idcache_wbinv_all(void);
#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
#elif defined(CPU_XSCALE_PXA2X0)
#define cpu_idcache_wbinv_all xscale_cache_purgeID
extern void xscale_cache_purgeID(void);
#elif defined(CPU_XSCALE_81342)

18
sys/arm/arm/identcpu-v4.c
View File

@ -119,13 +119,6 @@ static const char * const pxa27x_steppings[16] = {
"rev 12", "rev 13", "rev 14", "rev 15",
};
static const char * const ixp425_steppings[16] = {
"step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3",
"rev 4", "rev 5", "rev 6", "rev 7",
"rev 8", "rev 9", "rev 10", "rev 11",
"rev 12", "rev 13", "rev 14", "rev 15",
};
struct cpuidtab {
u_int32_t cpuid;
enum cpu_class cpu_class;
@ -200,17 +193,6 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210",
pxa2x0_steppings },
{ CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz",
ixp425_steppings },
{ CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz",
ixp425_steppings },
{ CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz",
ixp425_steppings },
/* XXX ixp435 steppings? */
{ CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435",
ixp425_steppings },
{ CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131",
generic_steppings },

147
sys/arm/conf/AVILA
View File

@ -1,147 +0,0 @@
# AVILA -- Gateworks Avila XScale board
# kernel configuration file for FreeBSD/arm
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
ident AVILA
include "std.arm"
include "../xscale/ixp425/std.ixp425"
# NB: memory mapping is defined in std.avila
include "../xscale/ixp425/std.avila"
options XSCALE_CACHE_READ_WRITE_ALLOCATE
#To statically compile in device wiring instead of /boot/device.hints
hints "AVILA.hints" # Default places to look for devices.
makeoptions MODULES_OVERRIDE=""
makeoptions CONF_CFLAGS=-mcpu=xscale
#options HZ=1000
options HZ=100
options DEVICE_POLLING
options SCHED_4BSD # 4BSD scheduler
options INET # InterNETworking
options TCP_HHOOK # hhook(9) framework for TCP
options GEOM_PART_BSD # BSD partition scheme
options GEOM_PART_MBR # MBR partition scheme
options TMPFS # Efficient memory filesystem
options FFS # Berkeley Fast Filesystem
options SOFTUPDATES # Enable FFS soft updates support
options NFSCL # Network Filesystem Client
options NFS_ROOT # NFS usable as /, requires NFSCL
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=npe0
#options BOOTP_WIRED_TO=ath0
#options BOOTP_WIRED_TO=rl0
options BOOTP_COMPAT
#options PREEMPTION
#options VERBOSE_SYSINIT
# Hardware performance counters
options HWPMC_HOOKS
device hwpmc
#device saarm
device pci
device uart
device ixpwdog # watchdog timer
device cfi # flash support
device cfid # flash disk support
device geom_redboot # redboot fis parser
# I2C Bus
device iicbus
device iicbb
device iic
device ixpiic # I2C bus glue
device ds1672 # DS1672 on I2C bus
device ad7418 # AD7418 on I2C bus
device avila_led
device gpio
device gpioled
device avila_gpio # GPIO pins on J8
device ata
device avila_ata # Gateworks CF/IDE support
device npe # Network Processing Engine
device npe_fw
device firmware
device qmgr # Q Manager (required by npe)
device mii # NB: required by npe
device ether
device bpf
device loop
device if_bridge
device md
device random # Entropy device
# Wireless NIC cards
device wlan # 802.11 support
options IEEE80211_DEBUG
options IEEE80211_SUPPORT_TDMA
options IEEE80211_SUPPORT_MESH
device wlan_wep # 802.11 WEP support
device wlan_ccmp # 802.11 CCMP support
device wlan_tkip # 802.11 TKIP support
device wlan_xauth
device ath # Atheros NICs
device ath_pci # Atheros pci/cardbus glue
options ATH_DEBUG
options ATH_DIAGAPI
#options ATH_TX99_DIAG
device ath_rate_sample # SampleRate tx rate control for ath
#options AH_DEBUG
#options AH_ASSERT
#device ath_ar5210
#device ath_ar5211
device ath_ar5212
device ath_rf2413
device ath_rf2417
device ath_rf2425
device ath_rf5111
device ath_rf5112
device ath_rf5413
#
device ath_ar5416
options AH_SUPPORT_AR5416
device ath_ar9160
device ath_ar9280
device usb
device ohci
device ehci
device umass
device scbus # SCSI bus (required for ATA/SCSI)
device da # Direct Access (disks)
device pass # Passthrough device (direct ATA/SCSI access)
#device ural
#device zyd
#device wlan_amrr

53
sys/arm/conf/AVILA.hints
View File

@ -1,53 +0,0 @@
# $FreeBSD$
#
# Device wiring for the Gateworks Avila 2384.
#
# DBGU is unit 0
hint.uart.0.at="ixp0"
hint.uart.0.addr=0xc8000000
hint.uart.0.irq=15
hint.uart.0.flags=0x10
hint.uart.0.ier_rxbits=0x5d # NB: need UUE+RTOIE
# USART0 is unit 1
hint.uart.1.at="ixp0"
hint.uart.1.addr=0xc8001000
hint.uart.1.irq=13
hint.uart.1.ier_rxbits=0x5d # NB: need UUE+RTOIE
# NPE Hardware Queue Manager
hint.ixpqmgr.0.at="ixp0"
# NPE wired NICs, requires ixpqmgr
hint.npe.0.at="ixp0"
hint.npe.0.npeid="B"
hint.npe.0.mac="B"
hint.npe.0.mii="B"
hint.npe.0.phy=0
hint.npe.1.at="ixp0"
hint.npe.1.npeid="C"
hint.npe.1.mac="C"
hint.npe.1.mii="B"
hint.npe.1.phy=1
# FLASH
hint.cfi.0.at="ixp0"
hint.cfi.0.addr=0x50000000
# CF IDE controller
hint.ata_avila.0.at="ixp0"
# Front Panel LED
hint.led_avila.0.at="ixp0"
# GPIO pins
hint.gpio_avila.0.at="ixp0"
# Analog Devices AD7418 temperature sensor
hint.ad7418.0.at="iicbus0"
hint.ad7418.0.addr=0x50
# Dallas Semiconductor DS1672 RTC
hint.ds1672_rtc.0.at="iicbus0"
hint.ds1672_rtc.0.addr=0xd0

141
sys/arm/conf/CAMBRIA
View File

@ -1,141 +0,0 @@
# CAMBRIA -- Gateworks Cambria 235x boards
# kernel configuration file for FreeBSD/arm
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
ident CAMBRIA
include "std.arm"
include "../xscale/ixp425/std.ixp435"
# NB: memory mapping is defined in std.avila
include "../xscale/ixp425/std.avila"
options XSCALE_CACHE_READ_WRITE_ALLOCATE
#To statically compile in device wiring instead of /boot/device.hints
hints "CAMBRIA.hints" # Default places to look for devices.
makeoptions CONF_CFLAGS=-mcpu=xscale
makeoptions MODULES_OVERRIDE=""
#options HZ=1000
options HZ=100
options DEVICE_POLLING
options SCHED_4BSD # 4BSD scheduler
#options PREEMPTION
options INET # InterNETworking
options TCP_HHOOK # hhook(9) framework for TCP
options GEOM_PART_BSD # BSD partition scheme
options GEOM_PART_MBR # MBR partition scheme
options TMPFS # Efficient memory filesystem
options FFS # Berkeley Fast Filesystem
options SOFTUPDATES # Enable FFS soft updates support
options NFSCL # Network Filesystem Client
options NFS_ROOT # NFS usable as /, requires NFSCL
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=npe0
options BOOTP_COMPAT
# Hardware performance counters
options HWPMC_HOOKS
device hwpmc
#options VERBOSE_SYSINIT
options VERBOSE_INIT_ARM
#device saarm
device pci
device uart
device ixpwdog # watchdog timer
options IXP4XX_FLASH_SIZE=0x02000000 # stock 2358 comes w/ 32M
device cfi # flash support
device cfid # flash disk support
device geom_redboot # redboot fis parser
# I2C Bus
device iicbus
device iicbb
device iic
device ixpiic # I2C bus glue
device ds1672 # DS1672 on I2C bus
device ad7418 # AD7418 on I2C bus
device cambria_fled # Font Panel LED on I2C bus
device cambria_led # 8-LED latch
device gpio
device gpioled
device cambria_gpio # GPIO pins on J11
device ata
device avila_ata # Gateworks CF/IDE support
device npe # Network Processing Engine
device npe_fw
device firmware
device qmgr # Q Manager (required by npe)
device mii # NB: required by npe
device ether
device bpf
device loop
device if_bridge
device md
device random # Entropy device
# Wireless NIC cards
device wlan # 802.11 support
options IEEE80211_DEBUG
options IEEE80211_SUPPORT_TDMA
options IEEE80211_SUPPORT_MESH
device wlan_wep # 802.11 WEP support
device wlan_ccmp # 802.11 CCMP support
device wlan_tkip # 802.11 TKIP support
device wlan_xauth
device ath # Atheros NICs
device ath_pci # Atheros pci/cardbus glue
options ATH_DEBUG
options ATH_DIAGAPI
options ATH_ENABLE_DFS
options ATH_ENABLE_11N
#options ATH_TX99_DIAG
device ath_rate_sample # SampleRate tx rate control for ath
options AH_DEBUG
options AH_PRIVATE_DIAG
options AH_SUPPORT_AR5416 # NB: for 11n descriptor format
device ath_hal
# NB: 2 USB 2.0 ports standard
device usb
options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
device ehci
device umass
device scbus # SCSI bus (required for ATA/SCSI)
device da # Direct Access (disks)
device pass # Passthrough device (direct ATA/SCSI access)
#device ural
#device zyd
#device wlan_amrr

75
sys/arm/conf/CAMBRIA.hints
View File

@ -1,75 +0,0 @@
# $FreeBSD$
#
# Device wiring for the Gateworks Cambria 2358.
#
# DBGU is unit 0
hint.uart.0.at="ixp0"
hint.uart.0.addr=0xc8000000
hint.uart.0.irq=15
hint.uart.0.flags=0x10
hint.uart.0.ier_rxbits=0x5d # NB: need UUE+RTOIE
# NB: no UART1 on ixp435
# optional GPS serial port
#hint.uart.1.at="ixp0"
#hint.uart.1.addr=0x53fc0000
#hint.uart.1.irq=20
#hint.uart.1.ier_rxbits=0x1
#hint.uart.1.rclk=1843200
# optional RS485 serial port
#hint.uart.2.at="ixp0"
#hint.uart.2.addr=0x53f80000
#hint.uart.2.irq=21
#hint.uart.2.rclk=1843200
# NPE Hardware Queue Manager
hint.ixpqmgr.0.at="ixp0"
# NPE wired NICs, requires ixpqmgr
hint.npe.0.at="ixp0"
hint.npe.0.npeid="C"
hint.npe.0.mac="C"
hint.npe.0.mii="C"
hint.npe.0.phy=1
hint.npe.1.at="ixp0"
hint.npe.1.npeid="A"
hint.npe.1.mac="A"
hint.npe.1.mii="C"
hint.npe.1.phy=2
# FLASH
hint.cfi.0.at="ixp0"
hint.cfi.0.addr=0x50000000
# CF IDE controller
hint.ata_avila.0.at="ixp0"
# Front Panel LED
hint.fled.0.at="iicbus0"
hint.fled.0.addr=0x5a
# Octal LED Latch
hint.led_cambria.0.at="ixp0"
# GPIO pins
hint.gpio_cambria.0.at="iicbus0"
hint.gpio_cambria.0.addr=0x56
# Analog Devices AD7418 temperature sensor
hint.ad7418.0.at="iicbus0"
hint.ad7418.0.addr=0x50
# Dallas Semiconductor DS1672 RTC
hint.ds1672_rtc.0.at="iicbus0"
hint.ds1672_rtc.0.addr=0xd0
# USB is part of the chip
hint.ehci.0.at="ixp0"
hint.ehci.0.addr=0xcd000000
hint.ehci.0.irq=32
hint.ehci.1.at="ixp0"
hint.ehci.1.addr=0xce000000
hint.ehci.1.irq=33

4
sys/arm/conf/NOTES
View File

@ -6,8 +6,6 @@ cpu CPU_ARM9
cpu CPU_ARM9E
cpu CPU_FA526
cpu CPU_XSCALE_81342
cpu CPU_XSCALE_IXP425
cpu CPU_XSCALE_IXP435
cpu CPU_XSCALE_PXA2X0
files "../at91/files.at91"
@ -19,8 +17,6 @@ files "../mv/orion/files.db88f5xxx"
files "../mv/orion/files.ts7800"
files "../xscale/i8134x/files.crb"
files "../xscale/i8134x/files.i81342"
files "../xscale/ixp425/files.avila"
files "../xscale/ixp425/files.ixp425"
files "../xscale/pxa/files.pxa"
options PHYSADDR=0x00000000

107
sys/arm/conf/NSLU
View File

@ -1,107 +0,0 @@
# NSLU - kernel configuration file for FreeBSD/arm on Linksys NSLU2
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
#NO_UNIVERSE
ident NSLU
include "std.arm"
# XXX What is defined in std.avila does not exactly match the following:
#options PHYSADDR=0x10000000
#options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
#options FLASHADDR=0x50000000
#options LOADERRAMADDR=0x00000000
include "../xscale/ixp425/std.ixp425"
# NB: memory mapping is defined in std.avila (see also comment above)
include "../xscale/ixp425/std.avila"
options XSCALE_CACHE_READ_WRITE_ALLOCATE
#To statically compile in device wiring instead of /boot/device.hints
hints "NSLU.hints" # Default places to look for devices.
makeoptions MODULES_OVERRIDE=""
makeoptions CONF_CFLAGS=-mcpu=xscale
options HZ=100
options DEVICE_POLLING
options SCHED_ULE # ULE scheduler
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options TCP_HHOOK # hhook(9) framework for TCP
options FFS # Berkeley Fast Filesystem
options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big directories
options NFSCL # Network Filesystem Client
options NFSD # Network Filesystem Server
options NFSLOCKD # Network Lock Manager
options NFS_ROOT # NFS usable as /, requires NFSCL
options GEOM_PART_BSD # BSD partition scheme
options GEOM_PART_MBR # MBR partition scheme
options TMPFS # Efficient memory filesystem
#options MSDOSFS # MSDOS Filesystem
options CD9660 # ISO 9660 Filesystem
#options PROCFS # Process filesystem (requires PSEUDOFS)
options PSEUDOFS # Pseudo-filesystem framework
options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI
options KTRACE # ktrace(1) support
options SYSVSHM # SYSV-style shared memory
options SYSVMSG # SYSV-style message queues
options SYSVSEM # SYSV-style semaphores
options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
options MUTEX_NOINLINE # Mutex inlines are space hogs
options RWLOCK_NOINLINE # rwlock inlines are space hogs
options SX_NOINLINE # sx inliens are space hogs
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=npe0
options BOOTP_COMPAT
device pci
device uart
# I2C Bus
device iicbus
device iicbb
device iic
device ixpiic # I2C bus glue
device ixpwdog # watchdog timer
device npe # Network Processing Engine
device npe_fw
device firmware
device qmgr # Q Manager (required by npe)
device mii # Minimal mii routines
device rlphy # NSLU2 uses Realtek PHY attached to npe
device ether
device bpf
device loop
device md
device random # Entropy device
device usb
device ohci
device ehci
device umass
device scbus # SCSI bus (required for ATA/SCSI)
device da # Direct Access (disks)

38
sys/arm/conf/NSLU.hints
View File

@ -1,38 +0,0 @@
# $FreeBSD$
#
# Device wiring for the Linksys NSLU2
#
# DBGU is unit 0
hint.uart.0.at="ixp0"
hint.uart.0.addr=0xc8000000
hint.uart.0.irq=15
hint.uart.0.flags=0x10
# USART0 is unit 1
hint.uart.1.at="ixp0"
hint.uart.1.addr=0xc8001000
hint.uart.1.irq=13
# NPE Hardware Queue Manager
hint.ixpqmgr.0.at="ixp0"
# NPE wired NICs, requires ixpqmgr
hint.npe.0.at="ixp0"
hint.npe.0.mac="B"
hint.npe.0.mii="B"
hint.npe.0.phy=1
# The second MAC isn't used on the NSLU, but it needs to be configured or
# we timeout on dhcp packets
hint.npe.1.at="ixp0"
#hint.npe.1.mac="B"
#hint.npe.1.mii="A"
#hint.npe.1.phy=0
#not yet
# RTC
#hint.xrtc.0.at="iicbus0"
#hint.xrtc.0.addr=0xde
# Slug LED
# Slug button
# Slug Buzzer

8
sys/arm/include/cpufunc.h
View File

@ -314,8 +314,7 @@ void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_FA526) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342)
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
void armv4_tlb_flushID (void);
void armv4_tlb_flushD (void);
@ -325,8 +324,7 @@ void armv4_drain_writebuf (void);
void armv4_idcache_inv_all (void);
#endif
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342)
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)
void xscale_cpwait (void);
void xscale_cpu_sleep (int mode);
@ -364,7 +362,7 @@ void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
void xscale_context_switch (void);
void xscale_setup (void);
#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#endif /* CPU_XSCALE_PXA2X0 */
#ifdef CPU_XSCALE_81342

3
sys/arm/include/intr.h
View File

@ -75,8 +75,7 @@ int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *);
#define NIRQ IRQ_GPIO_MAX
#elif defined(SOC_MV_DISCOVERY)
#define NIRQ 96
#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
defined(CPU_XSCALE_IXP435)
#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD)
#define NIRQ 64
#elif defined(CPU_CORTEXA)
#define NIRQ 1020

3
sys/arm/include/pmap-v4.h
View File

@ -63,8 +63,7 @@
#define ARM_MMU_GENERIC 0
#endif
#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342))
#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342))
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0

553
sys/arm/xscale/ixp425/avila_ata.c
View File

@ -1,553 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Compact Flash Support for the Avila Gateworks XScale boards.
* The CF slot is operated in "True IDE" mode. Registers are on
* the Expansion Bus connected to CS1 and CS2. Interrupts are
* tied to GPIO pin 12. No DMA, just PIO.
*
* The ADI Pronghorn Metro is very similar. It use CS3 and CS4 and
* GPIO pin 0 for interrupts.
*
* See also http://www.intel.com/design/network/applnots/302456.htm.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/time.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <sys/endian.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/intr.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <sys/ata.h>
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <vm/uma.h>
#include <dev/ata/ata-all.h>
#include <ata_if.h>
#define AVILA_IDE_CTRL 0x06
struct ata_config {
const char *desc; /* description for probe */
uint8_t gpin; /* GPIO pin */
uint8_t irq; /* IRQ */
uint32_t base16; /* CS base addr for 16-bit */
uint32_t size16; /* CS size for 16-bit */
uint32_t off16; /* CS offset for 16-bit */
uint32_t basealt; /* CS base addr for alt */
uint32_t sizealt; /* CS size for alt */
uint32_t offalt; /* CS offset for alt */
};
static const struct ata_config *
ata_getconfig(struct ixp425_softc *sa)
{
static const struct ata_config configs[] = {
{ .desc = "Gateworks Avila IDE/CF Controller",
.gpin = 12,
.irq = IXP425_INT_GPIO_12,
.base16 = IXP425_EXP_BUS_CS1_HWBASE,
.size16 = IXP425_EXP_BUS_CS1_SIZE,
.off16 = EXP_TIMING_CS1_OFFSET,
.basealt = IXP425_EXP_BUS_CS2_HWBASE,
.sizealt = IXP425_EXP_BUS_CS2_SIZE,
.offalt = EXP_TIMING_CS2_OFFSET,
},
{ .desc = "Gateworks Cambria IDE/CF Controller",
.gpin = 12,
.irq = IXP425_INT_GPIO_12,
.base16 = CAMBRIA_CFSEL0_HWBASE,
.size16 = CAMBRIA_CFSEL0_SIZE,
.off16 = EXP_TIMING_CS3_OFFSET,
.basealt = CAMBRIA_CFSEL1_HWBASE,
.sizealt = CAMBRIA_CFSEL1_SIZE,
.offalt = EXP_TIMING_CS4_OFFSET,
},
{ .desc = "ADI Pronghorn Metro IDE/CF Controller",
.gpin = 0,
.irq = IXP425_INT_GPIO_0,
.base16 = IXP425_EXP_BUS_CS3_HWBASE,
.size16 = IXP425_EXP_BUS_CS3_SIZE,
.off16 = EXP_TIMING_CS3_OFFSET,
.basealt = IXP425_EXP_BUS_CS4_HWBASE,
.sizealt = IXP425_EXP_BUS_CS4_SIZE,
.offalt = EXP_TIMING_CS4_OFFSET,
},
};
/* XXX honor hint? (but then no multi-board support) */
/* XXX total hack */
if (cpu_is_ixp43x())
return &configs[1]; /* Cambria */
if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0)
return &configs[0]; /* Avila */
return &configs[2]; /* Pronghorn */
}
struct ata_avila_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_exp_ioh; /* Exp Bus config registers */
bus_space_handle_t sc_ioh; /* CS1/3 data registers */
bus_space_handle_t sc_alt_ioh; /* CS2/4 data registers */
struct bus_space sc_expbus_tag;
struct resource sc_ata; /* hand-crafted for ATA */
struct resource sc_alt_ata; /* hand-crafted for ATA */
u_int32_t sc_16bit_off; /* EXP_TIMING_CSx_OFFSET */
int sc_rid; /* rid for IRQ */
struct resource *sc_irq; /* IRQ resource */
void *sc_ih; /* interrupt handler */
struct {
void (*cb)(void *);
void *arg;
} sc_intr[1]; /* NB: 1/channel */
};
static void ata_avila_intr(void *);
bs_protos(ata);
static void ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t,
u_int16_t *, bus_size_t);
static void ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t,
const u_int16_t *, bus_size_t);
static int
ata_avila_probe(device_t dev)
{
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
const struct ata_config *config;
config = ata_getconfig(sa);
if (config != NULL) {
device_set_desc_copy(dev, config->desc);
return 0;
}
return ENXIO;
}
static int
ata_avila_attach(device_t dev)
{
struct ata_avila_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
const struct ata_config *config;
config = ata_getconfig(sa);
KASSERT(config != NULL, ("no board config"));
sc->sc_dev = dev;
/* NB: borrow from parent */
sc->sc_iot = sa->sc_iot;
sc->sc_exp_ioh = sa->sc_exp_ioh;
if (bus_space_map(sc->sc_iot, config->base16, config->size16,
0, &sc->sc_ioh))
panic("%s: cannot map 16-bit window (0x%x/0x%x)",
__func__, config->base16, config->size16);
if (bus_space_map(sc->sc_iot, config->basealt, config->sizealt,
0, &sc->sc_alt_ioh))
panic("%s: cannot map alt window (0x%x/0x%x)",
__func__, config->basealt, config->sizealt);
sc->sc_16bit_off = config->off16;
if (config->base16 != CAMBRIA_CFSEL0_HWBASE) {
/*
* Craft special resource for ATA bus space ops
* that go through the expansion bus and require
* special hackery to ena/dis 16-bit operations.
*
* XXX probably should just make this generic for
* accessing the expansion bus.
*/
sc->sc_expbus_tag.bs_privdata = sc; /* NB: backpointer */
/* read single */
sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1;
sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2;
/* read multiple */
sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2;
sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s;
/* write (single) */
sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1;
sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2;
/* write multiple */
sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2;
sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s;
rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag);
rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag);
} else {
/*
* On Cambria use the shared CS3 expansion bus tag
* that handles interlock for sharing access with the
* optional UART's.
*/
rman_set_bustag(&sc->sc_ata, &cambria_exp_bs_tag);
rman_set_bustag(&sc->sc_alt_ata, &cambria_exp_bs_tag);
}
rman_set_bushandle(&sc->sc_ata, sc->sc_ioh);
rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh);
ixp425_set_gpio(sa, config->gpin, GPIO_TYPE_EDG_RISING);
/* configure CS1/3 window, leaving timing unchanged */
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* configure CS2/4 window, leaving timing unchanged */
EXP_BUS_WRITE_4(sc, config->offalt,
EXP_BUS_READ_4(sc, config->offalt) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* setup interrupt */
sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid,
config->irq, config->irq, 1, RF_ACTIVE);
if (!sc->sc_irq)
panic("Unable to allocate irq %u.\n", config->irq);
bus_setup_intr(dev, sc->sc_irq,
INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
NULL, ata_avila_intr, sc, &sc->sc_ih);
/* attach channel on this controller */
device_add_child(dev, "ata", -1);
bus_generic_attach(dev);
return 0;
}
static int
ata_avila_detach(device_t dev)
{
struct ata_avila_softc *sc = device_get_softc(dev);
/* XXX quiesce gpio? */
/* detach & delete all children */
device_delete_children(dev);
bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid, sc->sc_irq);
return 0;
}
static void
ata_avila_intr(void *xsc)
{
struct ata_avila_softc *sc = xsc;
if (sc->sc_intr[0].cb != NULL)
sc->sc_intr[0].cb(sc->sc_intr[0].arg);
}
static struct resource *
ata_avila_alloc_resource(device_t dev, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct ata_avila_softc *sc = device_get_softc(dev);
KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID,
("type %u rid %u start %ju end %ju count %ju flags %u",
type, *rid, start, end, count, flags));
/* doesn't matter what we return so reuse the real thing */
return sc->sc_irq;
}
static int
ata_avila_release_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID,
("type %u rid %u", type, rid));
return 0;
}
static int
ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq,
int flags, driver_filter_t *filt,
driver_intr_t *function, void *argument, void **cookiep)
{
struct ata_avila_softc *sc = device_get_softc(dev);
int unit = ((struct ata_channel *)device_get_softc(child))->unit;
KASSERT(unit == 0, ("unit %d", unit));
sc->sc_intr[unit].cb = function;
sc->sc_intr[unit].arg = argument;
*cookiep = sc;
return 0;
}
static int
ata_avila_teardown_intr(device_t dev, device_t child, struct resource *irq,
void *cookie)
{
struct ata_avila_softc *sc = device_get_softc(dev);
int unit = ((struct ata_channel *)device_get_softc(child))->unit;
KASSERT(unit == 0, ("unit %d", unit));
sc->sc_intr[unit].cb = NULL;
sc->sc_intr[unit].arg = NULL;
return 0;
}
/*
* Bus space accessors for CF-IDE PIO operations.
*/
/*
* Enable/disable 16-bit ops on the expansion bus.
*/
static __inline void
enable_16(struct ata_avila_softc *sc)
{
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) &~ EXP_BYTE_EN);
DELAY(100); /* XXX? */
}
static __inline void
disable_16(struct ata_avila_softc *sc)
{
DELAY(100); /* XXX? */
EXP_BUS_WRITE_4(sc, sc->sc_16bit_off,
EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN);
}
uint8_t
ata_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
struct ata_avila_softc *sc = tag->bs_privdata;
return bus_space_read_1(sc->sc_iot, h, o);
}
void
ata_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v)
{
struct ata_avila_softc *sc = tag->bs_privdata;
bus_space_write_1(sc->sc_iot, h, o, v);
}
uint16_t
ata_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
struct ata_avila_softc *sc = tag->bs_privdata;
uint16_t v;
enable_16(sc);
v = bus_space_read_2(sc->sc_iot, h, o);
disable_16(sc);
return v;
}
void
ata_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v)
{
struct ata_avila_softc *sc = tag->bs_privdata;
enable_16(sc);
bus_space_write_2(sc->sc_iot, h, o, v);
disable_16(sc);
}
void
ata_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct ata_avila_softc *sc = tag->bs_privdata;
enable_16(sc);
bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc);
}
void
ata_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct ata_avila_softc *sc = tag->bs_privdata;
enable_16(sc);
bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc);
}
/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
void
ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct ata_avila_softc *sc = tag->bs_privdata;
uint16_t v;
bus_size_t i;
enable_16(sc);
#if 1
for (i = 0; i < c; i++) {
v = bus_space_read_2(sc->sc_iot, h, o);
d[i] = bswap16(v);
}
#else
bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc);
}
void
ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct ata_avila_softc *sc = tag->bs_privdata;
bus_size_t i;
enable_16(sc);
#if 1
for (i = 0; i < c; i++)
bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
#else
bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc);
}
static device_method_t ata_avila_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ata_avila_probe),
DEVMETHOD(device_attach, ata_avila_attach),
DEVMETHOD(device_detach, ata_avila_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* bus methods */
DEVMETHOD(bus_alloc_resource, ata_avila_alloc_resource),
DEVMETHOD(bus_release_resource, ata_avila_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, ata_avila_setup_intr),
DEVMETHOD(bus_teardown_intr, ata_avila_teardown_intr),
{ 0, 0 }
};
devclass_t ata_avila_devclass;
static driver_t ata_avila_driver = {
"ata_avila",
ata_avila_methods,
sizeof(struct ata_avila_softc),
};
DRIVER_MODULE(ata_avila, ixp, ata_avila_driver, ata_avila_devclass, 0, 0);
MODULE_VERSION(ata_avila, 1);
MODULE_DEPEND(ata_avila, ata, 1, 1, 1);
static int
avila_channel_probe(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
ch->unit = 0;
ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE;
device_set_desc_copy(dev, "ATA channel 0");
return ata_probe(dev);
}
static int
avila_channel_attach(device_t dev)
{
struct ata_avila_softc *sc = device_get_softc(device_get_parent(dev));
struct ata_channel *ch = device_get_softc(dev);
int i;
for (i = 0; i < ATA_MAX_RES; i++)
ch->r_io[i].res = &sc->sc_ata;
ch->r_io[ATA_DATA].offset = ATA_DATA;
ch->r_io[ATA_FEATURE].offset = ATA_FEATURE;
ch->r_io[ATA_COUNT].offset = ATA_COUNT;
ch->r_io[ATA_SECTOR].offset = ATA_SECTOR;
ch->r_io[ATA_CYL_LSB].offset = ATA_CYL_LSB;
ch->r_io[ATA_CYL_MSB].offset = ATA_CYL_MSB;
ch->r_io[ATA_DRIVE].offset = ATA_DRIVE;
ch->r_io[ATA_COMMAND].offset = ATA_COMMAND;
ch->r_io[ATA_ERROR].offset = ATA_FEATURE;
/* NB: should be used only for ATAPI devices */
ch->r_io[ATA_IREASON].offset = ATA_COUNT;
ch->r_io[ATA_STATUS].offset = ATA_COMMAND;
/* NB: the control and alt status registers are special */
ch->r_io[ATA_ALTSTAT].res = &sc->sc_alt_ata;
ch->r_io[ATA_ALTSTAT].offset = AVILA_IDE_CTRL;
ch->r_io[ATA_CONTROL].res = &sc->sc_alt_ata;
ch->r_io[ATA_CONTROL].offset = AVILA_IDE_CTRL;
/* NB: by convention this points at the base of registers */
ch->r_io[ATA_IDX_ADDR].offset = 0;
ata_generic_hw(dev);
return ata_attach(dev);
}
static device_method_t avila_channel_methods[] = {
/* device interface */
DEVMETHOD(device_probe, avila_channel_probe),
DEVMETHOD(device_attach, avila_channel_attach),
DEVMETHOD(device_detach, ata_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, ata_suspend),
DEVMETHOD(device_resume, ata_resume),
{ 0, 0 }
};
driver_t avila_channel_driver = {
"ata",
avila_channel_methods,
sizeof(struct ata_channel),
};
DRIVER_MODULE(ata, ata_avila, avila_channel_driver, ata_devclass, 0, 0);

371
sys/arm/xscale/ixp425/avila_gpio.c
View File

@ -1,371 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
* Copyright (c) 2009, Luiz Otavio O Souza.
* Copyright (c) 2010, Andrew Thompson <thompsa@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* GPIO driver for Gateworks Avilia
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/gpio.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <dev/gpio/gpiobusvar.h>
#include "gpio_if.h"
#define GPIO_SET_BITS(sc, reg, bits) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, (reg)) | (bits))
#define GPIO_CLEAR_BITS(sc, reg, bits) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, (reg)) & ~(bits))
struct avila_gpio_softc {
device_t sc_dev;
device_t sc_busdev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
uint32_t sc_valid;
struct gpio_pin sc_pins[IXP4XX_GPIO_PINS];
};
struct avila_gpio_pin {
const char *name;
int pin;
int caps;
};
#define GPIO_PIN_IO (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)
static struct avila_gpio_pin avila_gpio_pins[] = {
{ "GPIO0", 0, GPIO_PIN_IO },
{ "GPIO1", 1, GPIO_PIN_IO },
{ "GPIO2", 2, GPIO_PIN_IO },
{ "GPIO3", 3, GPIO_PIN_IO },
{ "GPIO4", 4, GPIO_PIN_IO },
/*
* The following pins are connected to system devices and should not
* really be frobbed.
*/
#if 0
{ "SER_ENA", 5, GPIO_PIN_IO },
{ "I2C_SCL", 6, GPIO_PIN_IO },
{ "I2C_SDA", 7, GPIO_PIN_IO },
{ "PCI_INTD", 8, GPIO_PIN_IO },
{ "PCI_INTC", 9, GPIO_PIN_IO },
{ "PCI_INTB", 10, GPIO_PIN_IO },
{ "PCI_INTA", 11, GPIO_PIN_IO },
{ "ATA_INT", 12, GPIO_PIN_IO },
{ "PCI_RST", 13, GPIO_PIN_IO },
{ "PCI_CLK", 14, GPIO_PIN_OUTPUT },
{ "EX_CLK", 15, GPIO_PIN_OUTPUT },
#endif
};
#undef GPIO_PIN_IO
/*
* Helpers
*/
static void avila_gpio_pin_configure(struct avila_gpio_softc *sc,
struct gpio_pin *pin, uint32_t flags);
static int avila_gpio_pin_flags(struct avila_gpio_softc *sc, uint32_t pin);
/*
* Driver stuff
*/
static int avila_gpio_probe(device_t dev);
static int avila_gpio_attach(device_t dev);
static int avila_gpio_detach(device_t dev);
/*
* GPIO interface
*/
static device_t avila_gpio_get_bus(device_t);
static int avila_gpio_pin_max(device_t dev, int *maxpin);
static int avila_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
static int avila_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
*flags);
static int avila_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
static int avila_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
static int avila_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
static int avila_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
static int avila_gpio_pin_toggle(device_t dev, uint32_t pin);
static int
avila_gpio_pin_flags(struct avila_gpio_softc *sc, uint32_t pin)
{
uint32_t v;
v = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & (1 << pin);
return (v ? GPIO_PIN_INPUT : GPIO_PIN_OUTPUT);
}
static void
avila_gpio_pin_configure(struct avila_gpio_softc *sc, struct gpio_pin *pin,
unsigned int flags)
{
uint32_t mask;
mask = 1 << pin->gp_pin;
/*
* Manage input/output
*/
if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
IXP4XX_GPIO_LOCK();
pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
if (flags & GPIO_PIN_OUTPUT) {
pin->gp_flags |= GPIO_PIN_OUTPUT;
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOER, mask);
}
else {
pin->gp_flags |= GPIO_PIN_INPUT;
GPIO_SET_BITS(sc, IXP425_GPIO_GPOER, mask);
}
IXP4XX_GPIO_UNLOCK();
}
}
static device_t
avila_gpio_get_bus(device_t dev)
{
struct avila_gpio_softc *sc;
sc = device_get_softc(dev);
return (sc->sc_busdev);
}
static int
avila_gpio_pin_max(device_t dev, int *maxpin)
{
*maxpin = IXP4XX_GPIO_PINS - 1;
return (0);
}
static int
avila_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin)))
return (EINVAL);
*caps = sc->sc_pins[pin].gp_caps;
return (0);
}
static int
avila_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin)))
return (EINVAL);
IXP4XX_GPIO_LOCK();
/* refresh since we do not own all the pins */
sc->sc_pins[pin].gp_flags = avila_gpio_pin_flags(sc, pin);
*flags = sc->sc_pins[pin].gp_flags;
IXP4XX_GPIO_UNLOCK();
return (0);
}
static int
avila_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin)))
return (EINVAL);
memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME);
return (0);
}
static int
avila_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1 << pin;
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask))
return (EINVAL);
avila_gpio_pin_configure(sc, &sc->sc_pins[pin], flags);
return (0);
}
static int
avila_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1 << pin;
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask))
return (EINVAL);
IXP4XX_GPIO_LOCK();
if (value)
GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask);
else
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask);
IXP4XX_GPIO_UNLOCK();
return (0);
}
static int
avila_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin)))
return (EINVAL);
IXP4XX_GPIO_LOCK();
*val = (GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & (1 << pin)) ? 1 : 0;
IXP4XX_GPIO_UNLOCK();
return (0);
}
static int
avila_gpio_pin_toggle(device_t dev, uint32_t pin)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1 << pin;
int res;
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask))
return (EINVAL);
IXP4XX_GPIO_LOCK();
res = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & mask;
if (res)
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask);
else
GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask);
IXP4XX_GPIO_UNLOCK();
return (0);
}
static int
avila_gpio_probe(device_t dev)
{
device_set_desc(dev, "Gateworks Avila GPIO driver");
return (0);
}
static int
avila_gpio_attach(device_t dev)
{
#define N(a) (sizeof(a) / sizeof(a[0]))
struct avila_gpio_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
int i;
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
for (i = 0; i < N(avila_gpio_pins); i++) {
struct avila_gpio_pin *p = &avila_gpio_pins[i];
strncpy(sc->sc_pins[p->pin].gp_name, p->name, GPIOMAXNAME);
sc->sc_pins[p->pin].gp_pin = p->pin;
sc->sc_pins[p->pin].gp_caps = p->caps;
sc->sc_pins[p->pin].gp_flags = avila_gpio_pin_flags(sc, p->pin);
sc->sc_valid |= 1 << p->pin;
}
sc->sc_busdev = gpiobus_attach_bus(dev);
if (sc->sc_busdev == NULL)
return (ENXIO);
return (0);
#undef N
}
static int
avila_gpio_detach(device_t dev)
{
gpiobus_detach_bus(dev);
return(0);
}
static device_method_t gpio_avila_methods[] = {
DEVMETHOD(device_probe, avila_gpio_probe),
DEVMETHOD(device_attach, avila_gpio_attach),
DEVMETHOD(device_detach, avila_gpio_detach),
/* GPIO protocol */
DEVMETHOD(gpio_get_bus, avila_gpio_get_bus),
DEVMETHOD(gpio_pin_max, avila_gpio_pin_max),
DEVMETHOD(gpio_pin_getname, avila_gpio_pin_getname),
DEVMETHOD(gpio_pin_getflags, avila_gpio_pin_getflags),
DEVMETHOD(gpio_pin_getcaps, avila_gpio_pin_getcaps),
DEVMETHOD(gpio_pin_setflags, avila_gpio_pin_setflags),
DEVMETHOD(gpio_pin_get, avila_gpio_pin_get),
DEVMETHOD(gpio_pin_set, avila_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, avila_gpio_pin_toggle),
{0, 0},
};
static driver_t gpio_avila_driver = {
"gpio",
gpio_avila_methods,
sizeof(struct avila_gpio_softc),
};
static devclass_t gpio_avila_devclass;
DRIVER_MODULE(gpio_avila, ixp, gpio_avila_driver, gpio_avila_devclass, 0, 0);
MODULE_VERSION(gpio_avila, 1);

120
sys/arm/xscale/ixp425/avila_led.c
View File

@ -1,120 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Kevin Lo. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <dev/led/led.h>
#define GPIO_LED_STATUS 3
#define GPIO_LED_STATUS_BIT (1U << GPIO_LED_STATUS)
struct led_avila_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
struct cdev *sc_led;
};
static void
led_func(void *arg, int onoff)
{
struct led_avila_softc *sc = arg;
uint32_t reg;
IXP4XX_GPIO_LOCK();
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
if (onoff)
reg &= ~GPIO_LED_STATUS_BIT;
else
reg |= GPIO_LED_STATUS_BIT;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
IXP4XX_GPIO_UNLOCK();
}
static int
led_avila_probe(device_t dev)
{
device_set_desc(dev, "Gateworks Avila Front Panel LED");
return (0);
}
static int
led_avila_attach(device_t dev)
{
struct led_avila_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
/* Configure LED GPIO pin as output */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) &~ GPIO_LED_STATUS_BIT);
sc->sc_led = led_create(led_func, sc, "gpioled");
led_func(sc, 1); /* Turn on LED */
return (0);
}
static int
led_avila_detach(device_t dev)
{
struct led_avila_softc *sc = device_get_softc(dev);
if (sc->sc_led != NULL)
led_destroy(sc->sc_led);
return (0);
}
static device_method_t led_avila_methods[] = {
DEVMETHOD(device_probe, led_avila_probe),
DEVMETHOD(device_attach, led_avila_attach),
DEVMETHOD(device_detach, led_avila_detach),
{0, 0},
};
static driver_t led_avila_driver = {
"led_avila",
led_avila_methods,
sizeof(struct led_avila_softc),
};
static devclass_t led_avila_devclass;
DRIVER_MODULE(led_avila, ixp, led_avila_driver, led_avila_devclass, 0, 0);

419
sys/arm/xscale/ixp425/avila_machdep.c
View File

@ -1,419 +0,0 @@
/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependent functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_kstack_pages.h"
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/signalvar.h>
#include <sys/imgact.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/linker.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/cons.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/buf.h>
#include <sys/exec.h>
#include <sys/kdb.h>
#include <sys/msgbuf.h>
#include <sys/devmap.h>
#include <machine/physmem.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
#include <machine/machdep.h>
#include <machine/metadata.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <sys/reboot.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_IO 1
#define KERNEL_PT_IO_NUM 3
#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM
#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */
#define KERNEL_PT_AFKERNEL_NUM 9
/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
/* Physical and virtual addresses for some global pages */
struct pv_addr systempage;
struct pv_addr msgbufpv;
struct pv_addr irqstack;
struct pv_addr undstack;
struct pv_addr abtstack;
struct pv_addr kernelstack;
struct pv_addr minidataclean;
/* Static device mappings. */
static const struct devmap_entry ixp425_devmap[] = {
/* Physical/Virtual address for I/O space */
{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, },
/* Expansion Bus */
{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, },
/* CFI Flash on the Expansion Bus */
{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
IXP425_EXP_BUS_CS0_SIZE, },
/* IXP425 PCI Configuration */
{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, },
/* SDRAM Controller */
{ IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, },
/* PCI Memory Space */
{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, },
/* Q-Mgr Memory Space */
{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, },
{ 0 },
};
/* Static device mappings. */
static const struct devmap_entry ixp435_devmap[] = {
/* Physical/Virtual address for I/O space */
{ IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, },
{ IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, },
/* IXP425 PCI Configuration */
{ IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, },
/* DDRII Controller NB: mapped same place as IXP425 */
{ IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, },
/* PCI Memory Space */
{ IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, },
/* Q-Mgr Memory Space */
{ IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, },
/* CFI Flash on the Expansion Bus */
{ IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
IXP425_EXP_BUS_CS0_SIZE, },
/* USB1 Memory Space */
{ IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, },
/* USB2 Memory Space */
{ IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, },
/* GPS Memory Space */
{ CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, },
/* RS485 Memory Space */
{ CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, },
{ 0 }
};
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(struct arm_boot_params *abp)
{
#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
#define next_page(a) next_chunk2(a,PAGE_SIZE)
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize;
/* kernel text starts where we were loaded at boot */
#define KERNEL_TEXT_OFF (abp->abp_physaddr - PHYSADDR)
#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF)
#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF)
lastaddr = parse_boot_param(abp);
arm_physmem_kernaddr = abp->abp_physaddr;
set_cpufuncs(); /* NB: sets cputype */
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
init_static_kenv(NULL, 0);
/* Do basic tuning, hz etc */
init_param1();
/*
* We allocate memory downwards from where we were loaded
* by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
* entries in the L2 page table. Past that we re-align the
* allocation boundary so later data structures (stacks, etc)
* can be mapped with different attributes (write-back vs
* write-through). Note this leaves a gap for expansion
* (or might be repurposed).
*/
freemempos = abp->abp_physaddr;
/* macros to simplify initial memory allocation */
#define alloc_pages(var, np) do { \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
/* NB: this works because locore maps PA=VA */ \
memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
} while (0)
#define valloc_pages(var, np) do { \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + (KERNVIRTADDR - abp->abp_physaddr); \
} while (0)
/* force L1 page table alignment */
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
/* allocate contiguous L1 page table */
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
/* now allocate L2 page tables; they are linked to L1 below */
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa +
(KERNVIRTADDR - abp->abp_physaddr);
}
}
freemem_pt = freemempos; /* base of allocated pt's */
/*
* Re-align allocation boundary so we can map the area
* write-back instead of write-through for the stacks and
* related structures allocated below.
*/
freemempos = PHYSADDR + 0x100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, kstack_pages);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
/*
* Now construct the L1 page table. First map the L2
* page tables into the L1 so we can replace L1 mappings
* later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, rounddown2(ARM_VECTORS_HIGH, 0x00100000),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
&kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 1]);
pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 2]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = next_page((int)lastaddr);
afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
if (cpu_is_ixp43x())
devmap_bootstrap(l1pagetable, ixp435_devmap);
else
devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
cpu_setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptrs(0);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in cpu_setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
cpu_setup();
/* ready to setup the console (XXX move earlier if possible) */
cninit();
/*
* Fetch the RAM size from the MCU registers. The
* expansion bus was mapped above so we can now read 'em.
*/
if (cpu_is_ixp43x())
memsize = ixp435_ddram_size();
else
memsize = ixp425_sdram_size();
undefined_init();
init_proc0(kernelstack.pv_va);
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
vm_max_kernel_address = 0xe0000000;
pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
/*
* Add the physical ram we have available.
*
* Exclude the kernel, and all the things we allocated which immediately
* follow the kernel, from the VM allocation pool but not from crash
* dumps. virtual_avail is a global variable which tracks the kva we've
* "allocated" while setting up pmaps.
*
* Prepare the list of physical memory available to the vm subsystem.
*/
arm_physmem_hardware_region(PHYSADDR, memsize);
arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr -
freemem_pt, EXFLAG_NOALLOC);
arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 -
freemempos, EXFLAG_NOALLOC);
arm_physmem_exclude_region(abp->abp_physaddr,
virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
arm_physmem_init_kernel_globals();
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
#undef next_page
#undef next_chunk2
}

260
sys/arm/xscale/ixp425/cambria_exp_space.c
View File

@ -1,260 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Bus space tag for devices on the Cambria expansion bus.
* This interlocks accesses to allow the optional GPS+RS485 UART's
* to share access with the CF-IDE adapter. Note this does not
* slow the timing UART r/w ops because the lock operation does
* this implicitly for us. Also note we do not DELAY after byte/word
* chip select changes; this doesn't seem necessary (as required
* for IXP425/Avila boards).
*
* XXX should make this generic so all expansion bus devices can
* use it but probably not until we eliminate the ATA hacks
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(exp);
bs_protos(generic);
struct expbus_softc {
struct ixp425_softc *sc; /* bus space tag */
struct mtx lock; /* i/o interlock */
bus_size_t csoff; /* CS offset for 8/16 enable */
};
#define EXP_LOCK_INIT(exp) \
mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN)
#define EXP_LOCK_DESTROY(exp) \
mtx_destroy(&(exp)->lock)
#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock)
#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock)
/*
* Enable/disable 16-bit ops on the expansion bus.
*/
static __inline void
enable_16(struct ixp425_softc *sc, bus_size_t cs)
{
EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN);
}
static __inline void
disable_16(struct ixp425_softc *sc, bus_size_t cs)
{
EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN);
}
static uint8_t
cambria_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
uint8_t v;
EXP_LOCK(exp);
v = bus_space_read_1(sc->sc_iot, h, o);
EXP_UNLOCK(exp);
return v;
}
static void
cambria_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
bus_space_write_1(sc->sc_iot, h, o, v);
EXP_UNLOCK(exp);
}
static uint16_t
cambria_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
uint16_t v;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
v = bus_space_read_2(sc->sc_iot, h, o);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
return v;
}
static void
cambria_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_write_2(sc->sc_iot, h, o, v);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_read_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */
static void
cambria_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
uint16_t v;
bus_size_t i;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
#if 1
for (i = 0; i < c; i++) {
v = bus_space_read_2(sc->sc_iot, h, o);
d[i] = bswap16(v);
}
#else
bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
static void
cambria_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = tag->bs_privdata;
struct ixp425_softc *sc = exp->sc;
bus_size_t i;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
#if 1
for (i = 0; i < c; i++)
bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i]));
#else
bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c);
#endif
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
/* NB: we only define what's needed by ata+uart */
struct bus_space cambria_exp_bs_tag = {
/* mapping/unmapping */
.bs_map = generic_bs_map,
.bs_unmap = generic_bs_unmap,
/* barrier */
.bs_barrier = generic_bs_barrier,
/* read (single) */
.bs_r_1 = cambria_bs_r_1,
.bs_r_2 = cambria_bs_r_2,
/* write (single) */
.bs_w_1 = cambria_bs_w_1,
.bs_w_2 = cambria_bs_w_2,
/* read multiple */
.bs_rm_2 = cambria_bs_rm_2,
.bs_rm_2_s = cambria_bs_rm_2_s,
/* write multiple */
.bs_wm_2 = cambria_bs_wm_2,
.bs_wm_2_s = cambria_bs_wm_2_s,
};
void
cambria_exp_bus_init(struct ixp425_softc *sc)
{
static struct expbus_softc c3; /* NB: no need to malloc */
uint32_t cs3;
KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
c3.sc = sc;
c3.csoff = EXP_TIMING_CS3_OFFSET;
EXP_LOCK_INIT(&c3);
cambria_exp_bs_tag.bs_privdata = &c3;
cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
/* XXX force slowest possible timings and byte mode */
EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* XXX force GPIO 3+4 for GPS+RS485 uarts */
ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING);
ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING);
}

112
sys/arm/xscale/ixp425/cambria_fled.c
View File

@ -1,112 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2008 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Cambria Front Panel LED sitting on the I2C bus.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <dev/iicbus/iiconf.h>
#include <dev/led/led.h>
#include "iicbus_if.h"
#define IIC_M_WR 0 /* write operation */
#define LED_ADDR 0xae /* slave address */
struct fled_softc {
struct cdev *sc_led;
};
static int
fled_probe(device_t dev)
{
device_set_desc(dev, "Gateworks Cambria Front Panel LED");
return 0;
}
static void
fled_cb(void *arg, int onoff)
{
uint8_t data[1];
struct iic_msg msgs[1] = {
{ LED_ADDR, IIC_M_WR, 1, data },
};
device_t dev = arg;
data[0] = (onoff == 0); /* NB: low true */
(void) iicbus_transfer(dev, msgs, 1);
}
static int
fled_attach(device_t dev)
{
struct fled_softc *sc = device_get_softc(dev);
sc->sc_led = led_create(fled_cb, dev, "front");
fled_cb(dev, 1); /* Turn on LED */
return 0;
}
static int
fled_detach(device_t dev)
{
struct fled_softc *sc = device_get_softc(dev);
if (sc->sc_led != NULL)
led_destroy(sc->sc_led);
return 0;
}
static device_method_t fled_methods[] = {
DEVMETHOD(device_probe, fled_probe),
DEVMETHOD(device_attach, fled_attach),
DEVMETHOD(device_detach, fled_detach),
{0, 0},
};
static driver_t fled_driver = {
"fled",
fled_methods,
sizeof(struct fled_softc),
};
static devclass_t fled_devclass;
DRIVER_MODULE(fled, iicbus, fled_driver, fled_devclass, 0, 0);
MODULE_VERSION(fled, 1);
MODULE_DEPEND(fled, iicbus, 1, 1, 1);

505
sys/arm/xscale/ixp425/cambria_gpio.c
View File

@ -1,505 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2010, Andrew Thompson <thompsa@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* GPIO driver for Gateworks Cambria
*
* Note:
* The Cambria PLD does not set the i2c ack bit after each write, if we used the
* regular iicbus interface it would abort the xfer after the address byte
* times out and not write our latch. To get around this we grab the iicbus and
* then do our own bit banging. This is a compromise to changing all the iicbb
* device methods to allow a flag to be passed down and is similir to how Linux
* does it.
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/gpio.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <arm/xscale/ixp425/ixdp425reg.h>
#include <dev/gpio/gpiobusvar.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
#include "iicbb_if.h"
#include "gpio_if.h"
#define IIC_M_WR 0 /* write operation */
#define PLD_ADDR 0xac /* slave address */
#define I2C_DELAY 10
#define GPIO_CONF_CLR(sc, reg, mask) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
#define GPIO_CONF_SET(sc, reg, mask) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
#define GPIO_PINS 5
struct cambria_gpio_softc {
device_t sc_dev;
device_t sc_busdev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
struct mtx sc_mtx;
struct gpio_pin sc_pins[GPIO_PINS];
uint8_t sc_latch;
uint8_t sc_val;
};
struct cambria_gpio_pin {
const char *name;
int pin;
int flags;
};
extern struct ixp425_softc *ixp425_softc;
static struct cambria_gpio_pin cambria_gpio_pins[GPIO_PINS] = {
{ "PLD0", 0, GPIO_PIN_OUTPUT },
{ "PLD1", 1, GPIO_PIN_OUTPUT },
{ "PLD2", 2, GPIO_PIN_OUTPUT },
{ "PLD3", 3, GPIO_PIN_OUTPUT },
{ "PLD4", 4, GPIO_PIN_OUTPUT },
};
/*
* Helpers
*/
static int cambria_gpio_read(struct cambria_gpio_softc *, uint32_t, unsigned int *);
static int cambria_gpio_write(struct cambria_gpio_softc *);
/*
* Driver stuff
*/
static int cambria_gpio_probe(device_t dev);
static int cambria_gpio_attach(device_t dev);
static int cambria_gpio_detach(device_t dev);
/*
* GPIO interface
*/
static device_t cambria_gpio_get_bus(device_t);
static int cambria_gpio_pin_max(device_t dev, int *maxpin);
static int cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
static int cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
*flags);
static int cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
static int cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
static int cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
static int cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
static int cambria_gpio_pin_toggle(device_t dev, uint32_t pin);
static int
i2c_getsda(struct cambria_gpio_softc *sc)
{
uint32_t reg;
IXP4XX_GPIO_LOCK();
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
IXP4XX_GPIO_UNLOCK();
return (reg & GPIO_I2C_SDA_BIT);
}
static void
i2c_setsda(struct cambria_gpio_softc *sc, int val)
{
IXP4XX_GPIO_LOCK();
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
if (val)
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
else
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
IXP4XX_GPIO_UNLOCK();
DELAY(I2C_DELAY);
}
static void
i2c_setscl(struct cambria_gpio_softc *sc, int val)
{
IXP4XX_GPIO_LOCK();
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
if (val)
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
else
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
IXP4XX_GPIO_UNLOCK();
DELAY(I2C_DELAY);
}
static void
i2c_sendstart(struct cambria_gpio_softc *sc)
{
i2c_setsda(sc, 1);
i2c_setscl(sc, 1);
i2c_setsda(sc, 0);
i2c_setscl(sc, 0);
}
static void
i2c_sendstop(struct cambria_gpio_softc *sc)
{
i2c_setscl(sc, 1);
i2c_setsda(sc, 1);
i2c_setscl(sc, 0);
i2c_setsda(sc, 0);
}
static void
i2c_sendbyte(struct cambria_gpio_softc *sc, u_char data)
{
int i;
for (i=7; i>=0; i--) {
i2c_setsda(sc, data & (1<<i));
i2c_setscl(sc, 1);
i2c_setscl(sc, 0);
}
i2c_setscl(sc, 1);
i2c_getsda(sc);
i2c_setscl(sc, 0);
}
static u_char
i2c_readbyte(struct cambria_gpio_softc *sc)
{
int i;
unsigned char data=0;
for (i=7; i>=0; i--)
{
i2c_setscl(sc, 1);
if (i2c_getsda(sc))
data |= (1<<i);
i2c_setscl(sc, 0);
}
return data;
}
static int
cambria_gpio_read(struct cambria_gpio_softc *sc, uint32_t pin, unsigned int *val)
{
device_t dev = sc->sc_dev;
int error;
error = iicbus_request_bus(device_get_parent(dev), dev,
IIC_DONTWAIT);
if (error)
return (error);
i2c_sendstart(sc);
i2c_sendbyte(sc, PLD_ADDR | LSB);
*val = (i2c_readbyte(sc) & (1 << pin)) != 0;
i2c_sendstop(sc);
iicbus_release_bus(device_get_parent(dev), dev);
return (0);
}
static int
cambria_gpio_write(struct cambria_gpio_softc *sc)
{
device_t dev = sc->sc_dev;
int error;
error = iicbus_request_bus(device_get_parent(dev), dev,
IIC_DONTWAIT);
if (error)
return (error);
i2c_sendstart(sc);
i2c_sendbyte(sc, PLD_ADDR & ~LSB);
i2c_sendbyte(sc, sc->sc_latch);
i2c_sendstop(sc);
iicbus_release_bus(device_get_parent(dev), dev);
return (0);
}
static device_t
cambria_gpio_get_bus(device_t dev)
{
struct cambria_gpio_softc *sc;
sc = device_get_softc(dev);
return (sc->sc_busdev);
}
static int
cambria_gpio_pin_max(device_t dev, int *maxpin)
{
*maxpin = GPIO_PINS - 1;
return (0);
}
static int
cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
if (pin >= GPIO_PINS)
return (EINVAL);
*caps = sc->sc_pins[pin].gp_caps;
return (0);
}
static int
cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
if (pin >= GPIO_PINS)
return (EINVAL);
*flags = sc->sc_pins[pin].gp_flags;
return (0);
}
static int
cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
if (pin >= GPIO_PINS)
return (EINVAL);
memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME);
return (0);
}
static int
cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
int error;
uint8_t mask;
mask = 1 << pin;
if (pin >= GPIO_PINS)
return (EINVAL);
GPIO_LOCK(sc);
sc->sc_pins[pin].gp_flags = flags;
/*
* Writing a logical one sets the signal high and writing a logical
* zero sets the signal low. To configure a digital I/O signal as an
* input, a logical one must first be written to the data bit to
* three-state the associated output.
*/
if (flags & GPIO_PIN_INPUT || sc->sc_val & mask)
sc->sc_latch |= mask; /* input or output & high */
else
sc->sc_latch &= ~mask;
error = cambria_gpio_write(sc);
GPIO_UNLOCK(sc);
return (error);
}
static int
cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
int error;
uint8_t mask;
mask = 1 << pin;
if (pin >= GPIO_PINS)
return (EINVAL);
GPIO_LOCK(sc);
if (value)
sc->sc_val |= mask;
else
sc->sc_val &= ~mask;
if (sc->sc_pins[pin].gp_flags != GPIO_PIN_OUTPUT) {
/* just save, altering the latch will disable input */
GPIO_UNLOCK(sc);
return (0);
}
if (value)
sc->sc_latch |= mask;
else
sc->sc_latch &= ~mask;
error = cambria_gpio_write(sc);
GPIO_UNLOCK(sc);
return (error);
}
static int
cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
int error = 0;
if (pin >= GPIO_PINS)
return (EINVAL);
GPIO_LOCK(sc);
if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT)
*val = (sc->sc_latch & (1 << pin)) ? 1 : 0;
else
error = cambria_gpio_read(sc, pin, val);
GPIO_UNLOCK(sc);
return (error);
}
static int
cambria_gpio_pin_toggle(device_t dev, uint32_t pin)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
int error = 0;
if (pin >= GPIO_PINS)
return (EINVAL);
GPIO_LOCK(sc);
sc->sc_val ^= (1 << pin);
if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) {
sc->sc_latch ^= (1 << pin);
error = cambria_gpio_write(sc);
}
GPIO_UNLOCK(sc);
return (error);
}
static int
cambria_gpio_probe(device_t dev)
{
device_set_desc(dev, "Gateworks Cambria GPIO driver");
return (0);
}
static int
cambria_gpio_attach(device_t dev)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
int pin;
sc->sc_dev = dev;
sc->sc_iot = ixp425_softc->sc_iot;
sc->sc_gpio_ioh = ixp425_softc->sc_gpio_ioh;
mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
for (pin = 0; pin < GPIO_PINS; pin++) {
struct cambria_gpio_pin *p = &cambria_gpio_pins[pin];
strncpy(sc->sc_pins[pin].gp_name, p->name, GPIOMAXNAME);
sc->sc_pins[pin].gp_pin = pin;
sc->sc_pins[pin].gp_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
sc->sc_pins[pin].gp_flags = 0;
cambria_gpio_pin_setflags(dev, pin, p->flags);
}
sc->sc_busdev = gpiobus_attach_bus(dev);
if (sc->sc_busdev == NULL) {
mtx_destroy(&sc->sc_mtx);
return (ENXIO);
}
return (0);
}
static int
cambria_gpio_detach(device_t dev)
{
struct cambria_gpio_softc *sc = device_get_softc(dev);
KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
gpiobus_detach_bus(dev);
mtx_destroy(&sc->sc_mtx);
return(0);
}
static device_method_t cambria_gpio_methods[] = {
DEVMETHOD(device_probe, cambria_gpio_probe),
DEVMETHOD(device_attach, cambria_gpio_attach),
DEVMETHOD(device_detach, cambria_gpio_detach),
/* GPIO protocol */
DEVMETHOD(gpio_get_bus, cambria_gpio_get_bus),
DEVMETHOD(gpio_pin_max, cambria_gpio_pin_max),
DEVMETHOD(gpio_pin_getname, cambria_gpio_pin_getname),
DEVMETHOD(gpio_pin_getflags, cambria_gpio_pin_getflags),
DEVMETHOD(gpio_pin_getcaps, cambria_gpio_pin_getcaps),
DEVMETHOD(gpio_pin_setflags, cambria_gpio_pin_setflags),
DEVMETHOD(gpio_pin_get, cambria_gpio_pin_get),
DEVMETHOD(gpio_pin_set, cambria_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, cambria_gpio_pin_toggle),
{0, 0},
};
static driver_t cambria_gpio_driver = {
"gpio",
cambria_gpio_methods,
sizeof(struct cambria_gpio_softc),
};
static devclass_t cambria_gpio_devclass;
DRIVER_MODULE(gpio_cambria, iicbus, cambria_gpio_driver, cambria_gpio_devclass, 0, 0);
MODULE_VERSION(gpio_cambria, 1);
MODULE_DEPEND(gpio_cambria, iicbus, 1, 1, 1);

135
sys/arm/xscale/ixp425/cambria_led.c
View File

@ -1,135 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2008 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Gateworks Cambria Octal LED Latch driver.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <machine/armreg.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <dev/led/led.h>
struct led_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
struct cdev *sc_leds[8];
uint8_t sc_latch;
};
static void
update_latch(struct led_softc *sc, int bit, int onoff)
{
if (onoff)
sc->sc_latch &= ~bit;
else
sc->sc_latch |= bit;
bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_latch);
}
static void led_A(void *arg, int onoff) { update_latch(arg, 1<<0, onoff); }
static void led_B(void *arg, int onoff) { update_latch(arg, 1<<1, onoff); }
static void led_C(void *arg, int onoff) { update_latch(arg, 1<<2, onoff); }
static void led_D(void *arg, int onoff) { update_latch(arg, 1<<3, onoff); }
static void led_E(void *arg, int onoff) { update_latch(arg, 1<<4, onoff); }
static void led_F(void *arg, int onoff) { update_latch(arg, 1<<5, onoff); }
static void led_G(void *arg, int onoff) { update_latch(arg, 1<<6, onoff); }
static void led_H(void *arg, int onoff) { update_latch(arg, 1<<7, onoff); }
static int
led_probe(device_t dev)
{
device_set_desc(dev, "Gateworks Octal LED Latch");
return (0);
}
static int
led_attach(device_t dev)
{
struct led_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
/* NB: write anywhere works, use first location */
if (bus_space_map(sc->sc_iot, CAMBRIA_OCTAL_LED_HWBASE, sizeof(uint8_t),
0, &sc->sc_ioh)) {
device_printf(dev, "cannot map LED latch (0x%lx)",
CAMBRIA_OCTAL_LED_HWBASE);
return ENXIO;
}
sc->sc_leds[0] = led_create(led_A, sc, "A");
sc->sc_leds[1] = led_create(led_B, sc, "B");
sc->sc_leds[2] = led_create(led_C, sc, "C");
sc->sc_leds[3] = led_create(led_D, sc, "D");
sc->sc_leds[4] = led_create(led_E, sc, "E");
sc->sc_leds[5] = led_create(led_F, sc, "F");
sc->sc_leds[6] = led_create(led_G, sc, "G");
sc->sc_leds[7] = led_create(led_H, sc, "H");
return 0;
}
static int
led_detach(device_t dev)
{
struct led_softc *sc = device_get_softc(dev);
int i;
for (i = 0; i < 8; i++) {
struct cdev *led = sc->sc_leds[i];
if (led != NULL)
led_destroy(led);
}
return (0);
}
static device_method_t led_methods[] = {
DEVMETHOD(device_probe, led_probe),
DEVMETHOD(device_attach, led_attach),
DEVMETHOD(device_detach, led_detach),
{0, 0},
};
static driver_t led_driver = {
"led_cambria",
led_methods,
sizeof(struct led_softc),
};
static devclass_t led_devclass;
DRIVER_MODULE(led_cambria, ixp, led_driver, led_devclass, 0, 0);

10
sys/arm/xscale/ixp425/files.avila
View File

@ -1,10 +0,0 @@
#$FreeBSD$
arm/xscale/ixp425/avila_machdep.c standard
arm/xscale/ixp425/avila_ata.c optional avila_ata
arm/xscale/ixp425/avila_led.c optional avila_led
arm/xscale/ixp425/avila_gpio.c optional avila_gpio
arm/xscale/ixp425/cambria_exp_space.c standard
arm/xscale/ixp425/cambria_fled.c optional cambria_fled
arm/xscale/ixp425/cambria_led.c optional cambria_led
arm/xscale/ixp425/cambria_gpio.c optional cambria_gpio
arm/xscale/ixp425/ixdp425_pci.c optional pci

46
sys/arm/xscale/ixp425/files.ixp425
View File

@ -1,46 +0,0 @@
#$FreeBSD$
arm/xscale/ixp425/ixp425.c standard
arm/xscale/ixp425/ixp425_mem.c standard
arm/xscale/ixp425/ixp425_space.c standard
arm/xscale/ixp425/ixp425_timer.c standard
arm/xscale/ixp425/ixp425_wdog.c optional ixpwdog
arm/xscale/ixp425/ixp425_iic.c optional ixpiic
arm/xscale/ixp425/ixp425_pci.c optional pci
arm/xscale/ixp425/ixp425_pci_asm.S optional pci
arm/xscale/ixp425/ixp425_pci_space.c optional pci
arm/xscale/ixp425/uart_cpu_ixp425.c optional uart
arm/xscale/ixp425/uart_bus_ixp425.c optional uart
arm/xscale/ixp425/ixp425_a4x_space.c optional uart
arm/xscale/ixp425/ixp425_a4x_io.S optional uart
dev/cfi/cfi_bus_ixp4xx.c optional cfi
dev/uart/uart_dev_ns8250.c optional uart
#
# NPE-based Ethernet support (requires qmgr also).
#
arm/xscale/ixp425/if_npe.c optional npe
arm/xscale/ixp425/ixp425_npe.c optional npe
ixp425_npe_fw.c optional npe_fw \
compile-with "${AWK} -f $S/tools/fw_stub.awk IxNpeMicrocode.dat:npe_fw -mnpe -c${.TARGET}" \
no-implicit-rule before-depend local \
clean "ixp425_npe_fw.c"
#
# NB: ld encodes the path in the binary symbols generated for the
# firmware image so link the file to the object directory to
# get known values for reference in the _fw.c file.
#
IxNpeMicrocode.fwo optional npe_fw \
dependency "IxNpeMicrocode.dat" \
compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} IxNpeMicrocode.dat" \
no-implicit-rule \
clean "IxNpeMicrocode.fwo"
IxNpeMicrocode.dat optional npe_fw \
dependency "$S/contrib/dev/npe/IxNpeMicrocode.dat.uu" \
compile-with "uudecode < $S/contrib/dev/npe/IxNpeMicrocode.dat.uu" \
no-obj no-implicit-rule \
clean "IxNpeMicrocode.dat"
#
# Q-Manager support
#
arm/xscale/ixp425/ixp425_qmgr.c optional qmgr
#
dev/usb/controller/ehci_ixp4xx.c optional ehci usb

1781
sys/arm/xscale/ixp425/if_npe.c
View File

File diff suppressed because it is too large Load Diff

283
sys/arm/xscale/ixp425/if_npereg.h
View File

@ -1,283 +0,0 @@
/*-
* Copyright (c) 2006 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef ARM_XSCALE_IF_NPEREG_H
#define ARM_XSCALE_IF_NPEREG_H
/*
* NPE/NPE tx/rx descriptor format. This is just the area
* shared with ucode running in the NPE; the driver-specific
* state is defined in the driver. The shared area must be
* cacheline-aligned. We allocate NPE_MAXSEG "descriptors"
* per buffer; this allows us to do minimal s/g. The number
* of descriptors can be expanded but doing so uses memory
* so should be done with care.
*
* The driver sets up buffers in uncached memory.
*/
#define NPE_MAXSEG 3 /* empirically selected */
struct npehwbuf {
struct { /* NPE shared area, cacheline aligned */
uint32_t next; /* phys addr of next segment */
uint32_t len; /* buffer/segment length (bytes) */
uint32_t data; /* phys addr of data segment */
uint32_t pad[5]; /* pad to cacheline */
} ix_ne[NPE_MAXSEG];
};
#define NPE_FRAME_SIZE_DEFAULT 1536
#define NPE_FRAME_SIZE_MAX (65536-64)
#define NPE_FRAME_SIZE_MIN 64
/*
* Queue Manager-related definitions.
*
* These define the layout of 32-bit Q entries passed
* between the host cpu and the NPE's.
*/
#define NPE_QM_Q_NPE(e) (((e)>>0)&0x3) /* NPE ID */
#define NPE_QM_Q_PORT(e) (((e)>>3)&0x1) /* Port ID */
#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */
#define NPE_QM_Q_ADDR(e) ((e)&0xfffffffe0) /* phys address */
/*
* Host->NPE requests written to the shared mailbox.
* The NPE writes the same value back as an ACK.
*/
#define NPE_GETSTATUS 0x00 /* get firmware revision */
#define NPE_SETPORTADDRESS 0x01 /* set port id and mac address */
#define NPE_GETMACADDRDB 0x02 /* upload filter database */
#define NPE_SETMACADDRDB 0x03 /* download filter database */
#define NPE_GETSTATS 0x04 /* get statistics */
#define NPE_RESETSTATS 0x05 /* reset stats + return result */
#define NPE_SETMAXFRAME 0x06 /* configure max tx/rx frame lengths */
#define NPE_SETRXTAGMODE 0x07 /* configure VLAN rx operating mode */
#define NPE_SETDEFRXVID 0x08 /* set def VLAN tag + traffic class */
#define NPE_SETRXQOSENTRY 0x0b /* map user pri -> QoS class+rx qid */
#define NPE_SETFIREWALLMODE 0x0e /* config firewall services */
#define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */
/* ... XXX more */
#define NPE_MAC_MSGID_SHL 24
#define NPE_MAC_PORTID_SHL 16
/*
* MAC register definitions; see section
* 15.2 of the Intel Developers Manual.
*/
#define NPE_MAC_TX_CNTRL1 0x000
#define NPE_MAC_TX_CNTRL2 0x004
#define NPE_MAC_RX_CNTRL1 0x010
#define NPE_MAC_RX_CNTRL2 0x014
#define NPE_MAC_RANDOM_SEED 0x020
#define NPE_MAC_THRESH_P_EMPTY 0x030
#define NPE_MAC_THRESH_P_FULL 0x038
#define NPE_MAC_BUF_SIZE_TX 0x040
#define NPE_MAC_TX_DEFER 0x050
#define NPE_MAC_RX_DEFER 0x054
#define NPE_MAC_TX_TWO_DEFER_1 0x060
#define NPE_MAC_TX_TWO_DEFER_2 0x064
#define NPE_MAC_SLOT_TIME 0x070
#define NPE_MAC_MDIO_CMD_1 0x080
#define NPE_MAC_MDIO_CMD_2 0x084
#define NPE_MAC_MDIO_CMD_3 0x088
#define NPE_MAC_MDIO_CMD_4 0x08c
#define NPE_MAC_MDIO_STS_1 0x090
#define NPE_MAC_MDIO_STS_2 0x094
#define NPE_MAC_MDIO_STS_3 0x098
#define NPE_MAC_MDIO_STS_4 0x09c
#define NPE_MAC_ADDR_MASK_1 0x0A0
#define NPE_MAC_ADDR_MASK_2 0x0A4
#define NPE_MAC_ADDR_MASK_3 0x0A8
#define NPE_MAC_ADDR_MASK_4 0x0AC
#define NPE_MAC_ADDR_MASK_5 0x0B0
#define NPE_MAC_ADDR_MASK_6 0x0B4
#define NPE_MAC_ADDR_1 0x0C0
#define NPE_MAC_ADDR_2 0x0C4
#define NPE_MAC_ADDR_3 0x0C8
#define NPE_MAC_ADDR_4 0x0CC
#define NPE_MAC_ADDR_5 0x0D0
#define NPE_MAC_ADDR_6 0x0D4
#define NPE_MAC_INT_CLK_THRESH 0x0E0
#define NPE_MAC_UNI_ADDR_1 0x0F0
#define NPE_MAC_UNI_ADDR_2 0x0F4
#define NPE_MAC_UNI_ADDR_3 0x0F8
#define NPE_MAC_UNI_ADDR_4 0x0FC
#define NPE_MAC_UNI_ADDR_5 0x100
#define NPE_MAC_UNI_ADDR_6 0x104
#define NPE_MAC_CORE_CNTRL 0x1FC
#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2))
#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2))
#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2))
/*
* Bit definitions
*/
/* TX Control Register 1*/
#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */
#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */
#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */
#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */
#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */
#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */
#define NPE_TX_CNTRL1_RMII 0x40
/* TX Control Register 2 */
#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */
/* RX Control Register 1 */
#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */
#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */
#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */
#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */
#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */
#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */
#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */
#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */
/* RX Control Register 2 */
#define NPE_RX_CNTRL2_DEFER_EN 0x01
/* Core Control Register */
#define NPE_CORE_RESET 0x01 /* MAC reset state */
#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */
#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */
#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */
#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */
/*
* Stat block returned by NPE with NPE_GETSTATS msg.
*/
struct npestats {
uint32_t dot3StatsAlignmentErrors;
uint32_t dot3StatsFCSErrors;
uint32_t dot3StatsInternalMacReceiveErrors;
uint32_t RxOverrunDiscards;
uint32_t RxLearnedEntryDiscards;
uint32_t RxLargeFramesDiscards;
uint32_t RxSTPBlockedDiscards;
uint32_t RxVLANTypeFilterDiscards;
uint32_t RxVLANIdFilterDiscards;
uint32_t RxInvalidSourceDiscards;
uint32_t RxBlackListDiscards;
uint32_t RxWhiteListDiscards;
uint32_t RxUnderflowEntryDiscards;
uint32_t dot3StatsSingleCollisionFrames;
uint32_t dot3StatsMultipleCollisionFrames;
uint32_t dot3StatsDeferredTransmissions;
uint32_t dot3StatsLateCollisions;
uint32_t dot3StatsExcessiveCollisions;
uint32_t dot3StatsInternalMacTransmitErrors;
uint32_t dot3StatsCarrierSenseErrors;
uint32_t TxLargeFrameDiscards;
uint32_t TxVLANIdFilterDiscards;
};
/*
* Default values
*/
#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1
#define NPE_MAC_RESET_DELAY 1
/* This value applies to RMII */
#define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
/*
* MII definitions - these have been verified against the LXT971 and LXT972 PHYs
*/
#define NPE_MII_REG_SHL 16
#define NPE_MII_ADDR_SHL 21
/* NB: shorthands for mii bus mdio routines */
#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1
#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1
#define NPE_MII_GO (1<<31)
#define NPE_MII_WRITE (1<<26)
#define NPE_MII_TIMEOUT_10TH_SECS 5
#define NPE_MII_10TH_SEC_IN_MILLIS 100
#define NPE_MII_READ_FAIL (1<<31)
#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */
#define NPE_MII_PHY_NULL 0xff /* PHY is not present */
#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
/* Register definition */
#define NPE_MII_CTRL_REG 0x0 /* Control Register */
#define NPE_MII_STAT_REG 0x1 /* Status Register */
#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
#define NPE_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
#define NPE_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
/* Advertisement Register */
#define NPE_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
/* partner ability Register */
#define NPE_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
/* Expansion Register */
#define NPE_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
/* next-page transmit Register */
#endif /* ARM_XSCALE_IF_NPEREG_H */

169
sys/arm/xscale/ixp425/ixdp425_pci.c
View File

@ -1,169 +0,0 @@
/* $NetBSD: ixdp425_pci.c,v 1.6 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <dev/pci/pcivar.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <arm/xscale/ixp425/ixp425_intr.h>
#include <arm/xscale/ixp425/ixdp425reg.h>
void
ixp425_md_attach(device_t dev)
{
struct ixp425_softc *sc = device_get_softc(device_get_parent(dev));
struct ixppcib_softc *pci_sc = device_get_softc(dev);
uint32_t reg;
/* PCI Reset Assert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
reg &= ~(1U << GPIO_PCI_RESET);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
/* PCI Clock Disable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg &= ~GPCLKR_MUX14;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
/*
* set GPIO Direction
* Output: PCI_CLK, PCI_RESET
* Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
*/
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
reg &= ~(1U << GPIO_PCI_CLK);
reg &= ~(1U << GPIO_PCI_RESET);
reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
/*
* Set GPIO interrupt type
* PCI_INT_A, PCI_INTB, PCI_INT_C, PCI_INT_D: Active Low
*/
reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD));
reg &= ~GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_MASK);
reg |= GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_ACT_LOW);
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD), reg);
/* clear ISR */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
(1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
(1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
/* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
DELAY(1000);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg |
(0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT));
/* PCI Clock Enable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg |= GPCLKR_MUX14;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
/*
* wait 100us to satisfy "minimum reset assertion time from clock stable
* requirement of the PCI spec
*/
DELAY(100);
/* PCI Reset deassert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
reg |= 1U << GPIO_PCI_RESET;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
pci_sc->sc_irq_rman.rm_type = RMAN_ARRAY;
pci_sc->sc_irq_rman.rm_descr = "IXP425 PCI IRQs";
CTASSERT(PCI_INT_D < PCI_INT_A);
/* XXX this overlaps the irq's setup in ixp425_attach */
if (rman_init(&pci_sc->sc_irq_rman) != 0 ||
rman_manage_region(&pci_sc->sc_irq_rman, PCI_INT_D, PCI_INT_A) != 0)
panic("ixp425_md_attach: failed to set up IRQ rman");
}
#define IXP425_MAX_DEV 5
#define IXP425_MAX_LINE 4
int
ixp425_md_route_interrupt(device_t bridge, device_t device, int pin)
{
static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] = {
{PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
{PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
{PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
{PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
/* NB: for optional USB controller on Gateworks Avila */
{PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
};
int dev;
dev = pci_get_slot(device);
if (bootverbose)
device_printf(bridge, "routing pin %d for %s\n", pin,
device_get_nameunit(device));
if (pin >= 1 && pin <= IXP425_MAX_LINE &&
dev >= 1 && dev <= IXP425_MAX_DEV) {
return (ixp425_pci_table[dev - 1][pin - 1]);
} else
printf("ixppcib: no mapping for %d/%d/%d\n",
pci_get_bus(device), dev, pci_get_function(device));
return (-1);
}

50
sys/arm/xscale/ixp425/ixdp425reg.h
View File

@ -1,50 +0,0 @@
/* $NetBSD: ixdp425reg.h,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef _IXDP425REG_H_
#define _IXDP425REG_H_
/* GPIOs */
#define GPIO_PCI_CLK 14
#define GPIO_PCI_RESET 13
#define GPIO_PCI_INTA 11
#define GPIO_PCI_INTB 10
#define GPIO_PCI_INTC 9
#define GPIO_PCI_INTD 8
#define GPIO_I2C_SDA 7
#define GPIO_I2C_SDA_BIT (1U << GPIO_I2C_SDA)
#define GPIO_I2C_SCL 6
#define GPIO_I2C_SCL_BIT (1U << GPIO_I2C_SCL)
/* Interrupt */
#define PCI_INT_A IXP425_INT_GPIO_11
#define PCI_INT_B IXP425_INT_GPIO_10
#define PCI_INT_C IXP425_INT_GPIO_9
#define PCI_INT_D IXP425_INT_GPIO_8
#endif /* _IXDP425REG_H_ */

692
sys/arm/xscale/ixp425/ixp425.c
View File

@ -1,692 +0,0 @@
/* $NetBSD: ixp425.c,v 1.13 2009/10/21 14:15:50 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <arm/xscale/ixp425/ixp425_intr.h>
#include <dev/pci/pcireg.h>
volatile uint32_t intr_enabled;
uint32_t intr_steer = 0;
/* ixp43x et. al have +32 IRQ's */
volatile uint32_t intr_enabled2;
uint32_t intr_steer2 = 0;
struct ixp425_softc *ixp425_softc = NULL;
struct mtx ixp425_gpio_mtx;
static int ixp425_probe(device_t);
static void ixp425_identify(driver_t *, device_t);
static int ixp425_attach(device_t);
/*
* Return a mask of the "fuse" bits that identify
* which h/w features are present.
* NB: assumes the expansion bus is mapped.
*/
uint32_t
ixp4xx_read_feature_bits(void)
{
uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET);
bits &= ~EXP_FCTRL_RESVD;
if (!cpu_is_ixp46x())
bits &= ~EXP_FCTRL_IXP46X_ONLY;
return bits;
}
void
ixp4xx_write_feature_bits(uint32_t v)
{
IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v;
}
struct arm32_dma_range *
bus_dma_get_range(void)
{
return (NULL);
}
int
bus_dma_get_range_nb(void)
{
return (0);
}
static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */
0x00, 0x01, /* GPIO#0 -> GPIO#1 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */
0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */
0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */
0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */
0xff, 0xff /* INT#30 -> INT#31 */
};
static __inline uint32_t
ixp425_irq2gpio_bit(int irq)
{
return (1U << int2gpio[irq]);
}
#ifdef DDB
#include <ddb/ddb.h>
DB_SHOW_COMMAND(gpio, db_show_gpio)
{
static const char *itype[8] = {
[GPIO_TYPE_ACT_HIGH] = "act-high",
[GPIO_TYPE_ACT_LOW] = "act-low",
[GPIO_TYPE_EDG_RISING] = "edge-rising",
[GPIO_TYPE_EDG_FALLING] = "edge-falling",
[GPIO_TYPE_TRANSITIONAL]= "transitional",
[5] = "type-5", [6] = "type-6", [7] = "type-7"
};
uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR);
uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER);
uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR);
uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R);
uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R);
int i, j;
db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n",
gpoutr, gpinr, gpoer,
GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR));
db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n",
gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR));
for (i = 0; i < 16; i++) {
db_printf("[%2d] out %u in %u %-3s", i,
(gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out");
for (j = 0; j < 32; j++)
if (int2gpio[j] == i) {
db_printf(" irq %2u %s", j, itype[
(((i & 8) ? gpit2r : gpit1r) >> (3*(i&7)))
& 7]);
break;
}
db_printf("\n");
}
}
#endif
void
ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type)
{
uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin));
IXP4XX_GPIO_LOCK();
/* clear interrupt type */
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin),
gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK));
/* clear any pending interrupt */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<<pin));
/* set new interrupt type */
GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin),
gpiotr | GPIO_TYPE(pin, type));
/* configure gpio line as an input */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) | (1<<pin));
IXP4XX_GPIO_UNLOCK();
}
static __inline void
ixp425_gpio_ack(int irq)
{
if (irq < 32 && ((1 << irq) & IXP425_INT_GPIOMASK))
IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) =
ixp425_irq2gpio_bit(irq);
}
static void
ixp425_post_filter(void *arg)
{
uintptr_t irq = (uintptr_t) arg;
ixp425_gpio_ack(irq);
}
void
arm_mask_irq(uintptr_t nb)
{
int i;
i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled &= ~(1 << nb);
ixp425_set_intrmask();
} else {
intr_enabled2 &= ~(1 << (nb - 32));
ixp435_set_intrmask();
}
restore_interrupts(i);
/*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/
ixp425_gpio_ack(nb);
}
void
arm_unmask_irq(uintptr_t nb)
{
int i;
i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled |= (1 << nb);
ixp425_set_intrmask();
} else {
intr_enabled2 |= (1 << (nb - 32));
ixp435_set_intrmask();
}
restore_interrupts(i);
}
static __inline uint32_t
ixp425_irq_read(void)
{
return IXPREG(IXP425_INT_STATUS) & intr_enabled;
}
static __inline uint32_t
ixp435_irq_read(void)
{
return IXPREG(IXP435_INT_STATUS2) & intr_enabled2;
}
int
arm_get_next_irq(int last)
{
uint32_t mask;
last += 1; /* always advance fwd, NB: handles -1 */
if (last < 32) {
mask = ixp425_irq_read() >> last;
for (; mask != 0; mask >>= 1, last++) {
if (mask & 1)
return last;
}
last = 32;
}
if (cpu_is_ixp43x()) {
mask = ixp435_irq_read() >> (32-last);
for (; mask != 0; mask >>= 1, last++) {
if (mask & 1)
return last;
}
}
return -1;
}
void
cpu_reset(void)
{
bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK);
bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
IXP425_OST_WDOG, 0);
bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE,
IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA |
OST_WDOG_ENAB_CNT_ENA);
printf("Reset failed!\n");
for(;;);
}
static void
ixp425_identify(driver_t *driver, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "ixp", 0);
}
static int
ixp425_probe(device_t dev)
{
device_set_desc(dev, "Intel IXP4XX");
return (0);
}
static int
ixp425_attach(device_t dev)
{
struct ixp425_softc *sc;
device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS);
sc = device_get_softc(dev);
sc->sc_iot = &ixp425_bs_tag;
KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__));
ixp425_softc = sc;
intr_enabled = 0;
ixp425_set_intrmask();
ixp425_set_intrsteer();
if (cpu_is_ixp43x()) {
intr_enabled2 = 0;
ixp435_set_intrmask();
ixp435_set_intrsteer();
}
arm_post_filter = ixp425_post_filter;
mtx_init(&ixp425_gpio_mtx, "gpio", NULL, MTX_DEF);
if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
0, &sc->sc_gpio_ioh))
panic("%s: unable to map GPIO registers", __func__);
if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
0, &sc->sc_exp_ioh))
panic("%s: unable to map Expansion Bus registers", __func__);
/* XXX belongs in platform init */
if (cpu_is_ixp43x())
cambria_exp_bus_init(sc);
if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
NULL, NULL, &sc->sc_dmat))
panic("%s: failed to create dma tag", __func__);
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "IXP4XX IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0)
panic("%s: failed to set up IRQ rman", __func__);
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "IXP4XX Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0)
panic("%s: failed to set up memory rman", __func__);
BUS_ADD_CHILD(dev, 0, "pcib", 0);
BUS_ADD_CHILD(dev, 0, "ixpclk", 0);
BUS_ADD_CHILD(dev, 0, "ixpiic", 0);
/* XXX move to hints? */
BUS_ADD_CHILD(dev, 0, "ixpwdog", 0);
/* attach wired devices via hints */
bus_enumerate_hinted_children(dev);
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
static void
ixp425_hinted_child(device_t bus, const char *dname, int dunit)
{
device_t child;
struct ixp425_ivar *ivar;
child = BUS_ADD_CHILD(bus, 0, dname, dunit);
ivar = IXP425_IVAR(child);
resource_int_value(dname, dunit, "addr", &ivar->addr);
resource_int_value(dname, dunit, "irq", &ivar->irq);
}
static device_t
ixp425_add_child(device_t dev, u_int order, const char *name, int unit)
{
device_t child;
struct ixp425_ivar *ivar;
child = device_add_child_ordered(dev, order, name, unit);
if (child == NULL)
return NULL;
ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT);
if (ivar == NULL) {
device_delete_child(dev, child);
return NULL;
}
ivar->addr = 0;
ivar->irq = -1;
device_set_ivars(child, ivar);
return child;
}
static int
ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
{
struct ixp425_ivar *ivar = IXP425_IVAR(child);
switch (which) {
case IXP425_IVAR_ADDR:
if (ivar->addr != 0) {
*(uint32_t *)result = ivar->addr;
return 0;
}
break;
case IXP425_IVAR_IRQ:
if (ivar->irq != -1) {
*(int *)result = ivar->irq;
return 0;
}
break;
}
return EINVAL;
}
/*
* NB: This table handles P->V translations for regions setup with
* static mappings in initarm. This is used solely for calls to
* bus_alloc_resource_any; anything done with bus_space_map is
* handled elsewhere and does not require an entry here.
*
* XXX this table is also used by uart_cpu_getdev via getvbase
* (hence the public api)
*/
struct hwvtrans {
uint32_t hwbase;
uint32_t size;
uint32_t vbase;
int isa4x; /* XXX needs special bus space tag */
int isslow; /* XXX needs special bus space tag */
};
static const struct hwvtrans *
gethwvtrans(uint32_t hwbase, uint32_t size)
{
static const struct hwvtrans hwvtrans[] = {
/* NB: needed only for uart_cpu_getdev */
{ .hwbase = IXP425_UART0_HWBASE,
.size = IXP425_REG_SIZE,
.vbase = IXP425_UART0_VBASE,
.isa4x = 1 },
{ .hwbase = IXP425_UART1_HWBASE,
.size = IXP425_REG_SIZE,
.vbase = IXP425_UART1_VBASE,
.isa4x = 1 },
{ .hwbase = IXP425_PCI_HWBASE,
.size = IXP425_PCI_SIZE,
.vbase = IXP425_PCI_VBASE },
{ .hwbase = IXP425_PCI_MEM_HWBASE,
.size = IXP425_PCI_MEM_SIZE,
.vbase = IXP425_PCI_MEM_VBASE },
{ .hwbase = IXP425_EXP_BUS_CS0_HWBASE,
.size = IXP425_EXP_BUS_CS0_SIZE,
.vbase = IXP425_EXP_BUS_CS0_VBASE },
/* NB: needed for ixp435 ehci controllers */
{ .hwbase = IXP435_USB1_HWBASE,
.size = IXP435_USB1_SIZE,
.vbase = IXP435_USB1_VBASE },
{ .hwbase = IXP435_USB2_HWBASE,
.size = IXP435_USB2_SIZE,
.vbase = IXP435_USB2_VBASE },
{ .hwbase = CAMBRIA_GPS_HWBASE,
.size = CAMBRIA_GPS_SIZE,
.vbase = CAMBRIA_GPS_VBASE,
.isslow = 1 },
{ .hwbase = CAMBRIA_RS485_HWBASE,
.size = CAMBRIA_RS485_SIZE,
.vbase = CAMBRIA_RS485_VBASE,
.isslow = 1 },
};
int i;
for (i = 0; i < nitems(hwvtrans); i++) {
if (hwbase >= hwvtrans[i].hwbase &&
hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size)
return &hwvtrans[i];
}
return NULL;
}
/* XXX for uart_cpu_getdev */
int
getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase)
{
const struct hwvtrans *hw;
hw = gethwvtrans(hwbase, size);
if (hw == NULL)
return (ENOENT);
*vbase = hwbase - hw->hwbase + hw->vbase;
return (0);
}
static struct resource *
ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct ixp425_softc *sc = device_get_softc(dev);
const struct hwvtrans *vtrans;
struct resource *rv;
uint32_t addr;
int needactivate = flags & RF_ACTIVE;
int irq;
flags &= ~RF_ACTIVE;
switch (type) {
case SYS_RES_IRQ:
/* override per hints */
if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0)
start = end = irq;
rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count,
flags, child);
if (rv != NULL)
rman_set_rid(rv, *rid);
break;
case SYS_RES_MEMORY:
/* override per hints */
if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) {
start = addr;
/* XXX use nominal window to check for mapping */
vtrans = gethwvtrans(start, 0x1000);
if (vtrans != NULL) {
/*
* Assign the entire mapped region; this may
* not be correct but without more info from
* the caller we cannot tell.
*/
end = start + vtrans->size -
(start - vtrans->hwbase);
if (bootverbose)
device_printf(child,
"%s: assign 0x%jx:0x%jx%s\n",
__func__, start, end - start,
vtrans->isa4x ? " A4X" :
vtrans->isslow ? " SLOW" : "");
}
} else
vtrans = gethwvtrans(start, end - start);
if (vtrans == NULL) {
/* likely means above table needs to be updated */
device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n",
__func__, start, end - start);
return NULL;
}
rv = rman_reserve_resource(&sc->sc_mem_rman, start, end,
end - start, flags, child);
if (rv == NULL) {
device_printf(child, "%s: cannot reserve 0x%jx:0x%jx\n",
__func__, start, end - start);
return NULL;
}
rman_set_rid(rv, *rid);
break;
default:
rv = NULL;
break;
}
if (rv != NULL && needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
ixp425_release_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/* NB: no private resources, just release */
return rman_release_resource(r);
}
static int
ixp425_activate_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
struct ixp425_softc *sc = device_get_softc(dev);
const struct hwvtrans *vtrans;
if (type == SYS_RES_MEMORY) {
vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r));
if (vtrans == NULL) { /* NB: should not happen */
device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n",
__func__, rman_get_start(r), rman_get_size(r));
return (ENOENT);
}
if (vtrans->isa4x)
rman_set_bustag(r, &ixp425_a4x_bs_tag);
else if (vtrans->isslow)
rman_set_bustag(r, &cambria_exp_bs_tag);
else
rman_set_bustag(r, sc->sc_iot);
rman_set_bushandle(r, vtrans->vbase);
}
return (rman_activate_resource(r));
}
static int
ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/* NB: no private resources, just deactive */
return (rman_deactivate_resource(r));
}
static __inline void
get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2)
{
int i;
*mask = 0;
for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++)
*mask |= 1 << i;
*mask2 = 0;
for (; i <= rman_get_end(res); i++)
*mask2 |= 1 << (i - 32);
}
static __inline void
update_masks(uint32_t mask, uint32_t mask2)
{
intr_enabled = mask;
ixp425_set_intrmask();
if (cpu_is_ixp43x()) {
intr_enabled2 = mask2;
ixp435_set_intrmask();
}
}
static int
ixp425_setup_intr(device_t dev, device_t child,
struct resource *res, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
uint32_t mask, mask2;
int error;
error = BUS_SETUP_INTR(device_get_parent(dev), child, res, flags,
filt, intr, arg, cookiep);
if (error)
return (error);
get_masks(res, &mask, &mask2);
update_masks(intr_enabled | mask, intr_enabled2 | mask2);
return (0);
}
static int
ixp425_teardown_intr(device_t dev, device_t child, struct resource *res,
void *cookie)
{
uint32_t mask, mask2;
get_masks(res, &mask, &mask2);
update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2);
return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
}
static device_method_t ixp425_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ixp425_probe),
DEVMETHOD(device_attach, ixp425_attach),
DEVMETHOD(device_identify, ixp425_identify),
/* Bus interface */
DEVMETHOD(bus_add_child, ixp425_add_child),
DEVMETHOD(bus_hinted_child, ixp425_hinted_child),
DEVMETHOD(bus_read_ivar, ixp425_read_ivar),
DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource),
DEVMETHOD(bus_release_resource, ixp425_release_resource),
DEVMETHOD(bus_activate_resource, ixp425_activate_resource),
DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource),
DEVMETHOD(bus_setup_intr, ixp425_setup_intr),
DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr),
{0, 0},
};
static driver_t ixp425_driver = {
"ixp",
ixp425_methods,
sizeof(struct ixp425_softc),
};
static devclass_t ixp425_devclass;
DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0);

152
sys/arm/xscale/ixp425/ixp425_a4x_io.S
View File

@ -1,152 +0,0 @@
/* $NetBSD: ixp425_a4x_io.S,v 1.2 2005/12/11 12:16:51 christos Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* There are simple bus space functions for IO registers mapped at
* 32-bit aligned positions. offset is multiplied by 4.
*
* Based loosely on pxa2x0_a2x_io.S
*/
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
/*
* bus_space I/O functions with offset*4
*/
/*
* Read single
*/
ENTRY(a4x_bs_r_1)
ldr r0, [r1, r2, LSL #2]
and r0, r0, #0xff
mov pc, lr
END(a4x_bs_r_1)
ENTRY(a4x_bs_r_2)
ldr r0, [r1, r2, LSL #2]
mov r1, #0xff
orr r1, r1, r1, lsl #8
and r0, r0, r1
mov pc, lr
END(a4x_bs_r_2)
ENTRY(a4x_bs_r_4)
ldr r0, [r1, r2, LSL #2]
mov pc, lr
END(a4x_bs_r_4)
/*
* Write single
*/
ENTRY(a4x_bs_w_1)
and r3, r3, #0xff
str r3, [r1, r2, LSL #2]
mov pc, lr
END(a4x_bs_w_1)
ENTRY(a4x_bs_w_2)
mov r0, #0xff
orr r0, r0, r0, lsl #8
and r3, r3, r0
str r3, [r1, r2, LSL #2]
mov pc, lr
END(a4x_bs_w_2)
ENTRY(a4x_bs_w_4)
str r3, [r1, r2, LSL #2]
mov pc, lr
END(a4x_bs_w_4)
/*
* Read multiple
*/
ENTRY(a4x_bs_rm_1)
add r0, r1, r2, lsl #2
ldr r2, [sp, #0]
mov r1, r3
teq r2, #0
moveq pc, lr
1: ldr r3, [r0]
subs r2, r2, #1
strb r3, [r1], #1
bne 1b
mov pc, lr
END(a4x_bs_rm_1)
ENTRY(a4x_bs_rm_2)
add r0, r1, r2, lsl #2
ldr r2, [sp, #0]
mov r1, r3
teq r2, #0
moveq pc, lr
1: ldr r3, [r0]
subs r2, r2, #1
strh r3, [r1], #2
bne 1b
mov pc, lr
END(a4x_bs_rm_2)
/*
* Write multiple
*/
ENTRY(a4x_bs_wm_1)
add r0, r1, r2, lsl #2
ldr r2, [sp, #0]
mov r1, r3
teq r2, #0
moveq pc, lr
1: ldrb r3, [r1], #1
subs r2, r2, #1
str r3, [r0]
bne 1b
mov pc, lr
END(a4x_bs_wm_1)
ENTRY(a4x_bs_wm_2)
add r0, r1, r2, lsl #2
ldr r2, [sp, #0]
mov r1, r3
teq r2, #0
moveq pc, lr
1: ldrh r3, [r1], #2
subs r2, r2, #1
str r3, [r0]
bne 1b
mov pc, lr
END(a4x_bs_wm_2)

116
sys/arm/xscale/ixp425/ixp425_a4x_space.c
View File

@ -1,116 +0,0 @@
/* $NetBSD: ixp425_a4x_space.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Bus space tag for 8/16-bit devices on 32-bit bus.
* all registers are located at the address of multiple of 4.
*
* Based on pxa2x0_a4x_space.c
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(a4x);
bs_protos(generic);
struct bus_space ixp425_a4x_bs_tag = {
/* cookie */
.bs_privdata = (void *) 0,
/* mapping/unmapping */
.bs_map = generic_bs_map,
.bs_unmap = generic_bs_unmap,
.bs_subregion = generic_bs_subregion,
/* allocation/deallocation */
.bs_alloc = generic_bs_alloc, /* XXX not implemented */
.bs_free = generic_bs_free, /* XXX not implemented */
/* barrier */
.bs_barrier = generic_bs_barrier,
/* read (single) */
.bs_r_1 = a4x_bs_r_1,
.bs_r_2 = a4x_bs_r_2,
.bs_r_4 = a4x_bs_r_4,
/* read multiple */
.bs_rm_1 = a4x_bs_rm_1,
.bs_rm_2 = a4x_bs_rm_2,
/* read region */
/* XXX not implemented */
/* write (single) */
.bs_w_1 = a4x_bs_w_1,
.bs_w_2 = a4x_bs_w_2,
.bs_w_4 = a4x_bs_w_4,
/* write multiple */
.bs_wm_1 = a4x_bs_wm_1,
.bs_wm_2 = a4x_bs_wm_2,
/* write region */
/* XXX not implemented */
/* set multiple */
/* XXX not implemented */
/* set region */
/* XXX not implemented */
/* copy */
/* XXX not implemented */
};

197
sys/arm/xscale/ixp425/ixp425_iic.c
View File

@ -1,197 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Kevin Lo. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/uio.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <arm/xscale/ixp425/ixdp425reg.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
#include "iicbb_if.h"
#define I2C_DELAY 10
/* bit clr/set shorthands */
#define GPIO_CONF_CLR(sc, reg, mask) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask))
#define GPIO_CONF_SET(sc, reg, mask) \
GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask))
struct ixpiic_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
device_t iicbb;
};
static struct ixpiic_softc *ixpiic_sc = NULL;
static int
ixpiic_probe(device_t dev)
{
device_set_desc(dev, "IXP4XX GPIO-Based I2C Interface");
return (0);
}
static int
ixpiic_attach(device_t dev)
{
struct ixpiic_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
ixpiic_sc = sc;
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER,
GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR,
GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
/* add generic bit-banging code */
if ((sc->iicbb = device_add_child(dev, "iicbb", -1)) == NULL)
device_printf(dev, "could not add iicbb\n");
/* probe and attach the bit-banging code */
device_probe_and_attach(sc->iicbb);
return (0);
}
static int
ixpiic_callback(device_t dev, int index, caddr_t data)
{
return (0);
}
static int
ixpiic_getscl(device_t dev)
{
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
IXP4XX_GPIO_LOCK();
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
IXP4XX_GPIO_UNLOCK();
return (reg & GPIO_I2C_SCL_BIT);
}
static int
ixpiic_getsda(device_t dev)
{
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
IXP4XX_GPIO_LOCK();
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
IXP4XX_GPIO_UNLOCK();
return (reg & GPIO_I2C_SDA_BIT);
}
static void
ixpiic_setsda(device_t dev, int val)
{
struct ixpiic_softc *sc = ixpiic_sc;
IXP4XX_GPIO_LOCK();
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
if (val)
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
else
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
IXP4XX_GPIO_UNLOCK();
DELAY(I2C_DELAY);
}
static void
ixpiic_setscl(device_t dev, int val)
{
struct ixpiic_softc *sc = ixpiic_sc;
IXP4XX_GPIO_LOCK();
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
if (val)
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
else
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
IXP4XX_GPIO_UNLOCK();
DELAY(I2C_DELAY);
}
static int
ixpiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
{
/* reset bus */
ixpiic_setsda(dev, 1);
ixpiic_setscl(dev, 1);
return (IIC_ENOADDR);
}
static device_method_t ixpiic_methods[] = {
/* device interface */
DEVMETHOD(device_probe, ixpiic_probe),
DEVMETHOD(device_attach, ixpiic_attach),
/* iicbb interface */
DEVMETHOD(iicbb_callback, ixpiic_callback),
DEVMETHOD(iicbb_setsda, ixpiic_setsda),
DEVMETHOD(iicbb_setscl, ixpiic_setscl),
DEVMETHOD(iicbb_getsda, ixpiic_getsda),
DEVMETHOD(iicbb_getscl, ixpiic_getscl),
DEVMETHOD(iicbb_reset, ixpiic_reset),
{ 0, 0 }
};
static driver_t ixpiic_driver = {
"ixpiic",
ixpiic_methods,
sizeof(struct ixpiic_softc),
};
static devclass_t ixpiic_devclass;
DRIVER_MODULE(ixpiic, ixp, ixpiic_driver, ixpiic_devclass, 0, 0);
DRIVER_MODULE(iicbb, ixpiic, iicbb_driver, iicbb_devclass, 0, 0);

90
sys/arm/xscale/ixp425/ixp425_intr.h
View File

@ -1,90 +0,0 @@
/* $NetBSD: ixp425_intr.h,v 1.6 2005/12/24 20:06:52 perry Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IXP425_INTR_H_
#define _IXP425_INTR_H_
#define ARM_IRQ_HANDLER _C_LABEL(ixp425_intr_dispatch)
#ifndef _LOCORE
#include <machine/armreg.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#define IXPREG(reg) *((__volatile u_int32_t*) (reg))
void ixp425_do_pending(void);
extern __volatile uint32_t intr_enabled;
extern uint32_t intr_steer;
static __inline void __attribute__((__unused__))
ixp425_set_intrmask(void)
{
IXPREG(IXP425_INT_ENABLE) = intr_enabled & IXP425_INT_HWMASK;
}
static __inline void
ixp425_set_intrsteer(void)
{
IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK;
}
extern __volatile uint32_t intr_enabled2;
extern uint32_t intr_steer2;
static __inline void __attribute__((__unused__))
ixp435_set_intrmask(void)
{
IXPREG(IXP435_INT_ENABLE2) = intr_enabled2 & IXP435_INT_HWMASK;
}
static __inline void
ixp435_set_intrsteer(void)
{
IXPREG(IXP435_INT_SELECT2) = intr_steer2 & IXP435_INT_HWMASK;
}
#endif /* _LOCORE */
#endif /* _IXP425_INTR_H_ */

104
sys/arm/xscale/ixp425/ixp425_mem.c
View File

@ -1,104 +0,0 @@
/* $NetBSD: ixp425_mem.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
static uint32_t sdram_64bit[] = {
0x00800000, /* 8M: One 2M x 32 chip */
0x01000000, /* 16M: Two 2M x 32 chips */
0x01000000, /* 16M: Two 4M x 16 chips */
0x02000000, /* 32M: Four 4M x 32 chips */
0, 0, 0, 0
};
static uint32_t sdram_other[] = {
0x02000000, /* 32M: Two 8M x 16 chips */
0x04000000, /* 64M: Four 8M x 16 chips */
0x04000000, /* 64M: Two 16M x 16 chips */
0x08000000, /* 128M: Four 16M x 16 chips */
0x08000000, /* 128M: Two 32M x 16 chips */
0x10000000, /* 256M: Four 32M x 16 chips */
0, 0
};
uint32_t
ixp425_sdram_size(void)
{
#define MCU_REG_READ(x) (*(volatile uint32_t *)(IXP425_MCU_VBASE + (x)))
uint32_t size, sdr_config;
sdr_config = MCU_REG_READ(MCU_SDR_CONFIG);
if (sdr_config & MCU_SDR_CONFIG_64MBIT)
size = sdram_64bit[MCU_SDR_CONFIG_MCONF(sdr_config)];
else
size = sdram_other[MCU_SDR_CONFIG_MCONF(sdr_config)];
if (size == 0) {
printf("** SDR_CONFIG returns unknown value, using 32M\n");
size = 32 * 1024 * 1024;
}
return (size);
#undef MCU_REG_READ
}
uint32_t
ixp435_ddram_size(void)
{
#define MCU_REG_READ(x) (*(volatile uint32_t *)(IXP425_MCU_VBASE + (x)))
uint32_t sbr0;
/*
* Table 198, page 516 shows DDR-I/II SDRAM bank sizes
* for SBR0 and SBR1. The manual states both banks must
* be programmed to be the same size. We just assume
* it's done right and calculate 2x for the memory size.
*/
sbr0 = MCU_REG_READ(MCU_DDR_SBR0);
return 2 * 16*(sbr0 & 0x7f) * 1024 * 1024;
#undef MCU_REG_READ
}

1574
sys/arm/xscale/ixp425/ixp425_npe.c
View File

File diff suppressed because it is too large Load Diff

429
sys/arm/xscale/ixp425/ixp425_npereg.h
View File

@ -1,429 +0,0 @@
/*-
* SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-3-Clause)
*
* Copyright (c) 2006 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
/*-
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _IXP425_NPEREG_H_
#define _IXP425_NPEREG_H_
/* signature found as 1st word in a microcode image library */
#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF
/* marks end of header in a microcode image library */
#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF
/*
* Intel (R) IXP400 Software NPE Image ID Definition
*
* Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart()
* as input of type uint32_t which has the following fields format:
*
* Field [Bit Location]
* -----------------------------------
* Device ID [31 - 28]
* NPE ID [27 - 24]
* NPE Functionality ID [23 - 16]
* Major Release Number [15 - 8]
* Minor Release Number [7 - 0]
*/
#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \
(((imageId) >> 24) & 0xf)
#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \
(((imageId) >> 28) & 0xf)
#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \
(((imageId) >> 16) & 0xff)
#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \
(((imageId) >> 8) & 0xff)
#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \
(((imageId) >> 0) & 0xff)
/*
* Instruction and Data Memory Size (in words) for each NPE
*/
#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
#define IXP46X_NPEDL_INS_MEMSIZE_WORDS 4096
#define IXP46X_NPEDL_DATA_MEMSIZE_WORDS 4096
/* BAR offsets */
#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */
#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */
#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */
#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */
#define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */
#define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */
#define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */
#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */
#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */
#define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */
#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */
#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */
#define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */
#define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */
#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */
/*
* Reset value for Mailbox (MBST) register
* NOTE that if used, it should be complemented with an NPE instruction
* to clear the Mailbox at the NPE side as well
*/
#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */
#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */
#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */
/*
* EXCTL (Execution Control) Register commands
*/
#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */
#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */
#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */
#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */
/*
* Read/write operations use address in EXAD and data in EXDATA.
*/
#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */
#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */
#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */
#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */
#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */
#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */
#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */
/*
* EXCTL (Execution Control) Register status bit masks
*/
#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */
/*
* Executing Context Stack (ECS) level registers
*/
#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */
#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */
#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */
#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */
#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */
#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */
#define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */
/*
* Execution Access register reset values
*/
#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
/*
* Masks used to read/write particular bits in Execution Access registers
*/
#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */
#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */
#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */
#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */
#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */
#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */
/*
* Bit-Offsets from LSB of particular bit-fields in Execution Access registers.
*/
#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
/*
* NPE core & co-processor instruction templates to load into NPE Instruction
* Register, for read/write of NPE register file registers.
*/
/*
* Read an 8-bit NPE internal logical register
* and return the value in the EXDATA register (aligned to MSB).
* NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
*/
#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
/*
* Read a 16-bit NPE internal logical register
* and return the value in the EXDATA register (aligned to MSB).
* NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
*/
#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
/*
* Read a 16-bit NPE internal logical register
* and return the value in the EXDATA register.
* NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
*/
#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
/*
* Write an 8-bit NPE internal logical register.
* NPE Assembler instruction: "mov8 d0, #0"
*/
#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
/*
* Write a 16-bit NPE internal logical register.
* NPE Assembler instruction: "mov16 d0, #0"
*/
#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
/*
* Write a 16-bit NPE internal logical register.
* NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
*/
#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
/*
* Reset Mailbox (MBST) register
* NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
*/
#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
/*
* Bit-offsets from LSB, of particular bit-fields in an NPE instruction
*/
#define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */
#define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */
#define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */
/*
* Masks used to read/write particular bits of an NPE Instruction
*/
/**
* Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
* SRC field of immediate-mode NPE instruction
*/
#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
/**
* Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
* COPROC field of immediate-mode NPE instruction
*/
#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
/**
* LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
* to be used in COPROC field of immediate-mode NPE instruction
*/
#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
/**
* Number of left-shifts required to align most-sig 11 bits of 16-bit
* data value into COPROC field of immediate-mode NPE instruction
*/
#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
(IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
/**
* LDUR value used with immediate-mode NPE Instructions by the NpeDl
* for writing to NPE internal logical registers
*/
#define IX_NPEDL_WR_INSTR_LDUR 1
/**
* LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
* for reading from NPE internal logical registers
*/
#define IX_NPEDL_RD_INSTR_LDUR 0
/**
* NPE internal Context Store registers.
*/
typedef enum
{
IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
} IxNpeDlCtxtRegNum;
/*
* NPE Context Store register logical addresses
*/
#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
/*
* NPE Context Store register reset values
*/
/**
* Reset value of STEVT NPE internal Context Store register
* (STEVT = off, 0x80)
*/
#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
/**
* Reset value of STARTPC NPE internal Context Store register
* (STARTPC = 0x0000)
*/
#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
/**
* Reset value of REGMAP NPE internal Context Store register
* (REGMAP = d0->p0, d8->p2, d16->p4)
*/
#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
/**
* Reset value of CINDEX NPE internal Context Store register
* (CINDEX = 0)
*/
#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
/*
* Numeric range of context levels available on an NPE
*/
#define IX_NPEDL_CTXT_NUM_MIN 0
#define IX_NPEDL_CTXT_NUM_MAX 15
/**
* Number of Physical registers currently supported
* Initial NPE implementations will have a 32-word register file.
* Later implementations may have a 64-word register file.
*/
#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
/**
* LSB-offset of Regmap number in Physical NPE register address, used
* for Physical To Logical register address mapping in the NPE
*/
#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
/**
* Mask to extract a logical NPE register address from a physical
* register address, used for Physical To Logical address mapping
*/
#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
/*
* NPE Message/Mailbox interface.
*/
#define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */
#define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */
#define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */
/* control register */
#define IX_NPECTL_OFE 0x00010000 /* output fifo enable */
#define IX_NPECTL_IFE 0x00020000 /* input fifo enable */
#define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */
#define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */
/* status register */
#define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */
#define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */
#define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */
#define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */
#define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */
#define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */
#define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */
#define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */
#endif /* _IXP425_NPEREG_H_ */

124
sys/arm/xscale/ixp425/ixp425_npevar.h
View File

@ -1,124 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _IXP425_NPEVAR_H_
#define _IXP425_NPEVAR_H_
/*
* Intel (R) IXP400 Software NPE Image ID Definition
*
* Firmware Id's for current firmware image. These are typed by
* NPE ID and the feature set. Not all features are available
* on all NPE's. The Image ID has the following structure:
*
* Field [Bit Location]
* -----------------------------------
* Device ID [28..31]
* NPE ID [24..27]
* NPE Functionality ID [16..23]
* Major Release Number [8..15]
* Minor Release Number [0..7]
*
* The following "feature sets" are known to exist:
*
* HSS-0: supports 32 channelized and 4 packetized.
* HSS-0 + ATM + SPHY:
* For HSS, 16/32 channelized and 4/0 packetized.
* For ATM, AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs.
* Fast Path support.
* HSS-0 + ATM + MPHY:
* For HSS, 16/32 channelized and 4/0 packetized.
* For ATM, AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs.
* Fast Path support.
* ATM-Only:
* AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs.
* Fast Path support.
* HSS-2:
* HSS-0 and HSS-1.
* Each HSS port supports 32 channelized and 4 packetized.
* ETH: Ethernet Rx/Tx which includes:
* MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL
* ETH+VLAN Ethernet Rx/Tx which includes:
* MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS
* ETH+VLAN+HDR: Ethernet Rx/Tx which includes:
* SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION
*/
#define NPEIMAGE_DEVID(id) (((id) >> 28) & 0xf)
#define NPEIMAGE_NPEID(id) (((id) >> 24) & 0xf)
#define NPEIMAGE_FUNCID(id) (((id) >> 16) & 0xff)
#define NPEIMAGE_MAJOR(id) (((id) >> 8) & 0xff)
#define NPEIMAGE_MINOR(id) (((id) >> 0) & 0xff)
#define NPEIMAGE_MAKEID(dev, npe, func, maj, min) \
((((dev) & 0xf) << 28) | (((npe) & 0xf) << 24) | \
(((func) & 0xff) << 16) (((maj) & 0xff) << 8) | (((min) & 0xff) << 0))
/* XXX not right, revise */
/* NPE A Firmware Image Id's */
#define NPEFW_A_HSS0 0x00010000 /* HSS-0: 32 chan+4 packet */
#define NPEFW_A_HSS0_ATM_S_1 0x00020000 /* HSS-0+ATM UTOPIA SPHY (1 port) */
#define NPEFW_A_HSS0_ATM_M_1 0x00020000 /* HSS-0+ATM UTOPIA MPHY (1 port) */
#define NPEFW_A_ATM_M_12 0x00040000 /* ATM UTOPIA MPHY (12 ports) */
#define NPEFW_A_DMA 0x00150100 /* DMA only */
#define NPEFW_A_HSS2 0x00090000 /* HSS-0 + HSS-1 */
#define NPEFW_A_ETH 0x10800200 /* Basic Ethernet */
#define NPEFW_A_ETH_VLAN 0x10810200 /* NPEFW_A_ETH + VLAN QoS */
#define NPEFW_A_ETH_VLAN_HDR 0x10820200 /* NPEFW_A_ETH_VLAN + Hdr conv */
/* XXX ... more not included */
/* NPE B Firmware Image Id's */
#define NPEFW_B_ETH 0x01000200 /* Basic Ethernet */
#define NPEFW_B_ETH_VLAN 0x01010200 /* NPEFW_B_ETH + VLAN QoS */
#define NPEFW_B_ETH_VLAN_HDR 0x01020201 /* NPEFW_B_ETH_VLAN + Hdr conv */
#define NPEFW_B_DMA 0x01020100 /* DMA only */
/* XXX ... more not include */
/* NPE ID's */
#define NPE_A 0
#define NPE_B 1
#define NPE_C 2
#define NPE_MAX (NPE_C+1)
#define IXP425_NPE_A_IMAGEID 0x10820200
#define IXP425_NPE_B_IMAGEID 0x01000201
#define IXP425_NPE_C_IMAGEID 0x02000201
struct ixpnpe_softc;
struct ixpnpe_softc *ixpnpe_attach(device_t, int npeid);
void ixpnpe_detach(struct ixpnpe_softc *);
int ixpnpe_stopandreset(struct ixpnpe_softc *);
int ixpnpe_start(struct ixpnpe_softc *);
int ixpnpe_stop(struct ixpnpe_softc *);
int ixpnpe_init(struct ixpnpe_softc *);
int ixpnpe_getfunctionality(struct ixpnpe_softc *sc);
int ixpnpe_sendmsg_async(struct ixpnpe_softc *, const uint32_t msg[2]);
int ixpnpe_recvmsg_async(struct ixpnpe_softc *, uint32_t msg[2]);
int ixpnpe_sendandrecvmsg_sync(struct ixpnpe_softc *,
const uint32_t send[2], uint32_t recv[2]);
int ixpnpe_recvmsg_sync(struct ixpnpe_softc *, uint32_t msg[2]);
#endif /* _IXP425_NPEVAR_H_ */

477
sys/arm/xscale/ixp425/ixp425_pci.c
View File

@ -1,477 +0,0 @@
/* $NetBSD: ixp425_pci.c,v 1.6 2009/10/21 14:15:50 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <dev/pci/pcivar.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
#include <dev/pci/pcireg.h>
extern struct ixp425_softc *ixp425_softc;
#define PCI_CSR_WRITE_4(sc, reg, data) \
bus_write_4(sc->sc_csr, reg, data)
#define PCI_CSR_READ_4(sc, reg) \
bus_read_4(sc->sc_csr, reg)
#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
static device_probe_t ixppcib_probe;
static device_attach_t ixppcib_attach;
static bus_read_ivar_t ixppcib_read_ivar;
static bus_write_ivar_t ixppcib_write_ivar;
static bus_setup_intr_t ixppcib_setup_intr;
static bus_teardown_intr_t ixppcib_teardown_intr;
static bus_alloc_resource_t ixppcib_alloc_resource;
static bus_activate_resource_t ixppcib_activate_resource;
static bus_deactivate_resource_t ixppcib_deactivate_resource;
static bus_release_resource_t ixppcib_release_resource;
static pcib_maxslots_t ixppcib_maxslots;
static pcib_read_config_t ixppcib_read_config;
static pcib_write_config_t ixppcib_write_config;
static pcib_route_interrupt_t ixppcib_route_interrupt;
static int
ixppcib_probe(device_t dev)
{
device_set_desc(dev, "IXP4XX PCI Bus");
return (0);
}
static void
ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg,
uint32_t data)
{
PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE));
PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data);
}
static int
ixppcib_attach(device_t dev)
{
int rid;
struct ixppcib_softc *sc;
sc = device_get_softc(dev);
rid = 0;
sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE,
IXP425_PCI_SIZE, RF_ACTIVE);
if (sc->sc_csr == NULL)
panic("cannot allocate PCI CSR registers");
ixp425_md_attach(dev);
/* always setup the base, incase another OS messes w/ it */
PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b);
rid = 0;
sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE,
IXP425_PCI_MEM_SIZE, RF_ACTIVE);
if (sc->sc_mem == NULL)
panic("cannot allocate PCI MEM space");
/* NB: PCI dma window is 64M so anything above must be bounced */
if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
NULL, NULL, &sc->sc_dmat))
panic("couldn't create the PCI dma tag !");
/*
* Initialize the bus space tags.
*/
ixp425_io_bs_init(&sc->sc_pci_iot, sc);
ixp425_mem_bs_init(&sc->sc_pci_memt, sc);
sc->sc_dev = dev;
/* Initialize memory and i/o rmans. */
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman, 0,
IXP425_PCI_IO_SIZE) != 0) {
panic("ixppcib_probe: failed to set up I/O rman");
}
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE,
IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) {
panic("ixppcib_probe: failed to set up memory rman");
}
/*
* PCI->AHB address translation
* begin at the physical memory start + OFFSET
*/
PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE,
(IXP425_AHB_OFFSET & 0xFF000000) +
((IXP425_AHB_OFFSET & 0xFF000000) >> 8) +
((IXP425_AHB_OFFSET & 0xFF000000) >> 16) +
((IXP425_AHB_OFFSET & 0xFF000000) >> 24) +
0x00010203);
#define IXPPCIB_WRITE_CONF(sc, reg, val) \
ixp425_pci_conf_reg_write(sc, reg, val)
/* Write Mapping registers PCI Configuration Registers */
/* Base Address 0 - 3 */
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000);
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000);
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000);
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000);
/* Base Address 4 */
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff);
/* Base Address 5 */
IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000);
/* Assert some PCI errors */
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE);
#ifdef __ARMEB__
/*
* Set up byte lane swapping between little-endian PCI
* and the big-endian AHB bus
*/
PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS);
#else
PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE);
#endif
/*
* Enable bus mastering and I/O,memory access
*/
IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
/*
* Wait some more to ensure PCI devices have stabilised.
*/
DELAY(50000);
device_add_child(dev, "pci", -1);
return (bus_generic_attach(dev));
}
static int
ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct ixppcib_softc *sc;
sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = sc->sc_bus;
return (0);
}
return (ENOENT);
}
static int
ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
{
struct ixppcib_softc *sc;
sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
return (EINVAL);
case PCIB_IVAR_BUS:
sc->sc_bus = value;
return (0);
}
return (ENOENT);
}
static int
ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
void **cookiep)
{
return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
filt, intr, arg, cookiep));
}
static int
ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
void *cookie)
{
return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie));
}
static struct resource *
ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct ixppcib_softc *sc = device_get_softc(bus);
struct rman *rmanp;
struct resource *rv;
rv = NULL;
switch (type) {
case SYS_RES_IRQ:
rmanp = &sc->sc_irq_rman;
break;
case SYS_RES_IOPORT:
rmanp = &sc->sc_io_rman;
break;
case SYS_RES_MEMORY:
rmanp = &sc->sc_mem_rman;
break;
default:
return (rv);
}
rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE,
child);
if (rv == NULL)
return (NULL);
rman_set_rid(rv, *rid);
if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
struct ixppcib_softc *sc = device_get_softc(bus);
int error;
error = rman_activate_resource(r);
if (error)
return (error);
switch (type) {
case SYS_RES_IOPORT:
rman_set_bustag(r, &sc->sc_pci_iot);
rman_set_bushandle(r, rman_get_start(r));
break;
case SYS_RES_MEMORY:
rman_set_bustag(r, &sc->sc_pci_memt);
rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) +
(rman_get_start(r) - IXP425_PCI_MEM_HWBASE));
break;
}
return (0);
}
static int
ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
device_printf(bus, "%s called deactivate_resource (unexpected)\n",
device_get_nameunit(child));
return (ENXIO);
}
static int
ixppcib_release_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
device_printf(bus, "%s called release_resource (unexpected)\n",
device_get_nameunit(child));
return (ENXIO);
}
static bus_dma_tag_t
ixppcib_get_dma_tag(device_t bus, device_t child)
{
struct ixppcib_softc *sc = device_get_softc(bus);
return (sc->sc_dmat);
}
static void
ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func,
int reg)
{
if (bus == 0) {
/* configuration type 0 */
PCI_CSR_WRITE_4(sc, PCI_NP_AD,
(1U << (32 - (slot & 0x1f))) |
((func & 0x7) << 8) | (reg & ~3));
} else {
/* configuration type 1 */
PCI_CSR_WRITE_4(sc, PCI_NP_AD,
(bus << 16) | (slot << 11) |
(func << 8) | (reg & ~3) | 1);
}
}
static int
ixppcib_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static u_int32_t
ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
int bytes)
{
struct ixppcib_softc *sc = device_get_softc(dev);
u_int32_t data, ret;
ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ);
ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA);
ret >>= (reg & 3) * 8;
ret &= 0xffffffff >> ((4 - bytes) * 8);
#if 0
device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
__func__, bus, slot, func, reg, bytes, ret);
#endif
/* check & clear PCI abort */
data = PCI_CSR_READ_4(sc, PCI_ISR);
if (data & ISR_PFE) {
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
return (-1);
}
return (ret);
}
static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 };
static void
ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
u_int32_t val, int bytes)
{
struct ixppcib_softc *sc = device_get_softc(dev);
u_int32_t data;
#if 0
device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n",
__func__, bus, slot, func, reg, bytes, val);
#endif
ixppcib_conf_setup(sc, bus, slot, func, reg & ~3);
/* Byte enables are active low, so not them first */
PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE |
(~(byteenables[bytes] << (reg & 3)) & 0xf0));
PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8));
/* check & clear PCI abort */
data = PCI_CSR_READ_4(sc, PCI_ISR);
if (data & ISR_PFE)
PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE);
}
static int
ixppcib_route_interrupt(device_t bridge, device_t device, int pin)
{
return (ixp425_md_route_interrupt(bridge, device, pin));
}
static device_method_t ixppcib_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ixppcib_probe),
DEVMETHOD(device_attach, ixppcib_attach),
/* Bus interface */
DEVMETHOD(bus_read_ivar, ixppcib_read_ivar),
DEVMETHOD(bus_write_ivar, ixppcib_write_ivar),
DEVMETHOD(bus_setup_intr, ixppcib_setup_intr),
DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr),
DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource),
DEVMETHOD(bus_activate_resource, ixppcib_activate_resource),
DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource),
DEVMETHOD(bus_release_resource, ixppcib_release_resource),
DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag),
/* pcib interface */
DEVMETHOD(pcib_maxslots, ixppcib_maxslots),
DEVMETHOD(pcib_read_config, ixppcib_read_config),
DEVMETHOD(pcib_write_config, ixppcib_write_config),
DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt),
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
DEVMETHOD_END
};
static driver_t ixppcib_driver = {
"pcib",
ixppcib_methods,
sizeof(struct ixppcib_softc),
};
static devclass_t ixppcib_devclass;
DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0);

108
sys/arm/xscale/ixp425/ixp425_pci_asm.S
View File

@ -1,108 +0,0 @@
/* $NetBSD: ixp425_pci_asm.S,v 1.2 2005/12/11 12:16:51 christos Exp $ */
/*
* Copyright (c) 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#include <machine/asm.h>
/*
* Bus space functions for IXP425 PCI space access. We have to swizzle
* the address for 1 and 2 byte accesses when in big-endian mode.
*/
/*
* read single
*/
ENTRY(ixp425_pci_mem_bs_r_1)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x3
ldrb r0, [r1]
#else
ldrb r0, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
END(ixp425_pci_mem_bs_r_1)
ENTRY(ixp425_pci_mem_bs_r_2)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x2
ldrh r0, [r1]
#else
ldrh r0, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
END(ixp425_pci_mem_bs_r_2)
ENTRY(ixp425_pci_mem_bs_r_4)
ldr r0, [r1, r2]
mov pc, lr
END(ixp425_pci_mem_bs_r_4)
/*
* write single
*/
ENTRY(ixp425_pci_mem_bs_w_1)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x3
strb r3, [r1]
#else
strb r3, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
END(ixp425_pci_mem_bs_w_1)
ENTRY(ixp425_pci_mem_bs_w_2)
#ifdef __ARMEB__
add r1, r1, r2
eor r1, r1, #0x2
strh r3, [r1]
#else
strh r3, [r1, r2]
#endif /* __ARMEB__ */
mov pc, lr
END(ixp425_pci_mem_bs_w_2)
ENTRY(ixp425_pci_mem_bs_w_4)
str r3, [r1, r2]
mov pc, lr
END(ixp425_pci_mem_bs_w_4)

481
sys/arm/xscale/ixp425/ixp425_pci_space.c
View File

@ -1,481 +0,0 @@
/* $NetBSD: ixp425_pci_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* bus_space PCI functions for ixp425
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
/*
* Macros to read/write registers
*/
#define CSR_READ_4(x) *(volatile uint32_t *) \
(IXP425_PCI_CSR_BASE + (x))
#define CSR_WRITE_4(x, v) *(volatile uint32_t *) \
(IXP425_PCI_CSR_BASE + (x)) = (v)
/* Proto types for all the bus_space structure functions */
bs_protos(ixp425_pci);
bs_protos(ixp425_pci_io);
bs_protos(ixp425_pci_mem);
/* special I/O functions */
static u_int8_t _pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int16_t _pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int32_t _pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void _pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t);
static void _pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t);
static void _pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t);
#ifdef __ARMEB__
static u_int8_t _pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int16_t _pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int32_t _pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void _pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t);
static void _pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t);
static void _pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t);
static u_int8_t _pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int16_t _pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static u_int32_t _pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void _pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t);
static void _pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t);
static void _pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t);
#endif
struct bus_space ixp425_pci_io_bs_tag_template = {
/* mapping/unmapping */
.bs_map = ixp425_pci_io_bs_map,
.bs_unmap = ixp425_pci_io_bs_unmap,
.bs_subregion = ixp425_pci_bs_subregion,
.bs_alloc = ixp425_pci_io_bs_alloc,
.bs_free = ixp425_pci_io_bs_free,
/* barrier */
.bs_barrier = ixp425_pci_bs_barrier,
/*
* IXP425 processor does not have PCI I/O windows
*/
/* read (single) */
.bs_r_1 = _pci_io_bs_r_1,
.bs_r_2 = _pci_io_bs_r_2,
.bs_r_4 = _pci_io_bs_r_4,
/* write (single) */
.bs_w_1 = _pci_io_bs_w_1,
.bs_w_2 = _pci_io_bs_w_2,
.bs_w_4 = _pci_io_bs_w_4,
#ifdef __ARMEB__
.bs_r_1_s = _pci_io_bs_r_1_s,
.bs_r_2_s = _pci_io_bs_r_2_s,
.bs_r_4_s = _pci_io_bs_r_4_s,
.bs_w_1_s = _pci_io_bs_w_1_s,
.bs_w_2_s = _pci_io_bs_w_2_s,
.bs_w_4_s = _pci_io_bs_w_4_s,
#else
.bs_r_1_s = _pci_io_bs_r_1,
.bs_r_2_s = _pci_io_bs_r_2,
.bs_r_4_s = _pci_io_bs_r_4,
.bs_w_1_s = _pci_io_bs_w_1,
.bs_w_2_s = _pci_io_bs_w_2,
.bs_w_4_s = _pci_io_bs_w_4,
#endif
};
void
ixp425_io_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_pci_io_bs_tag_template;
bs->bs_privdata = cookie;
}
struct bus_space ixp425_pci_mem_bs_tag_template = {
/* mapping/unmapping */
.bs_map = ixp425_pci_mem_bs_map,
.bs_unmap = ixp425_pci_mem_bs_unmap,
.bs_subregion = ixp425_pci_bs_subregion,
.bs_alloc = ixp425_pci_mem_bs_alloc,
.bs_free = ixp425_pci_mem_bs_free,
/* barrier */
.bs_barrier = ixp425_pci_bs_barrier,
#ifdef __ARMEB__
/* read (single) */
.bs_r_1_s = _pci_mem_bs_r_1,
.bs_r_2_s = _pci_mem_bs_r_2,
.bs_r_4_s = _pci_mem_bs_r_4,
.bs_r_1 = ixp425_pci_mem_bs_r_1,
.bs_r_2 = ixp425_pci_mem_bs_r_2,
.bs_r_4 = ixp425_pci_mem_bs_r_4,
/* write (single) */
.bs_w_1_s = _pci_mem_bs_w_1,
.bs_w_2_s = _pci_mem_bs_w_2,
.bs_w_4_s = _pci_mem_bs_w_4,
.bs_w_1 = ixp425_pci_mem_bs_w_1,
.bs_w_2 = ixp425_pci_mem_bs_w_2,
.bs_w_4 = ixp425_pci_mem_bs_w_4,
#else
/* read (single) */
.bs_r_1 = ixp425_pci_mem_bs_r_1,
.bs_r_2 = ixp425_pci_mem_bs_r_2,
.bs_r_4 = ixp425_pci_mem_bs_r_4,
.bs_r_1_s = ixp425_pci_mem_bs_r_1,
.bs_r_2_s = ixp425_pci_mem_bs_r_2,
.bs_r_4_s = ixp425_pci_mem_bs_r_4,
/* write (single) */
.bs_w_1 = ixp425_pci_mem_bs_w_1,
.bs_w_2 = ixp425_pci_mem_bs_w_2,
.bs_w_4 = ixp425_pci_mem_bs_w_4,
.bs_w_1_s = ixp425_pci_mem_bs_w_1,
.bs_w_2_s = ixp425_pci_mem_bs_w_2,
.bs_w_4_s = ixp425_pci_mem_bs_w_4,
#endif
};
void
ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = ixp425_pci_mem_bs_tag_template;
bs->bs_privdata = cookie;
}
/* common routine */
int
ixp425_pci_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void
ixp425_pci_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* NULL */
}
/* io bs */
int
ixp425_pci_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size,
int cacheable, bus_space_handle_t *bshp)
{
*bshp = bpa;
return (0);
}
void
ixp425_pci_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
{
/* Nothing to do. */
}
int
ixp425_pci_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_pci_io_bs_alloc(): not implemented\n");
}
void
ixp425_pci_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_pci_io_bs_free(): not implemented\n");
}
/* special I/O functions */
static __inline u_int32_t
_bs_r(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t be)
{
u_int32_t data;
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
data = CSR_READ_4(PCI_NP_RDATA);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
return data;
}
static u_int8_t
_pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
data = _bs_r(tag, ioh, off, be);
return data >> (8 * n);
}
static u_int16_t
_pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = _bs_r(tag, ioh, off, be);
return data >> (8 * n);
}
static u_int32_t
_pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data;
data = _bs_r(tag, ioh, off, 0);
return data;
}
#ifdef __ARMEB__
static u_int8_t
_pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
data = _bs_r(tag, ioh, off, be);
return data >> (8 * n);
}
static u_int16_t
_pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = _bs_r(tag, ioh, off, be);
return data >> (8 * n);
}
static u_int32_t
_pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data;
data = _bs_r(tag, ioh, off, 0);
return le32toh(data);
}
#endif /* __ARMEB__ */
static __inline void
_bs_w(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int32_t be, u_int32_t data)
{
CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
CSR_WRITE_4(PCI_NP_WDATA, data);
if (CSR_READ_4(PCI_ISR) & ISR_PFE)
CSR_WRITE_4(PCI_ISR, ISR_PFE);
}
static void
_pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int8_t val)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
data = val << (8 * n);
_bs_w(tag, ioh, off, be, data);
}
static void
_pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int16_t val)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = val << (8 * n);
_bs_w(tag, ioh, off, be, data);
}
static void
_pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int32_t val)
{
_bs_w(tag, ioh, off, 0, val);
}
#ifdef __ARMEB__
static void
_pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int8_t val)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
data = val << (8 * n);
_bs_w(tag, ioh, off, be, data);
}
static void
_pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int16_t val)
{
u_int32_t data, n, be;
n = (ioh + off) % 4;
be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
data = val << (8 * n);
_bs_w(tag, ioh, off, be, data);
}
static void
_pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int32_t val)
{
_bs_w(tag, ioh, off, 0, htole32(val));
}
#endif /* __ARMEB__ */
/* mem bs */
int
ixp425_pci_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size,
int cacheable, bus_space_handle_t *bshp)
{
*bshp = (vm_offset_t)pmap_mapdev(bpa, size);
return (0);
}
void
ixp425_pci_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
{
pmap_unmapdev((vm_offset_t)h, size);
}
int
ixp425_pci_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("ixp425_mem_bs_alloc(): not implemented\n");
}
void
ixp425_pci_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_mem_bs_free(): not implemented\n");
}
#ifdef __ARMEB__
static u_int8_t
_pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
return ixp425_pci_mem_bs_r_1(tag, ioh, off);
}
static u_int16_t
_pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
return (ixp425_pci_mem_bs_r_2(tag, ioh, off));
}
static u_int32_t
_pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off)
{
u_int32_t data;
data = ixp425_pci_mem_bs_r_4(tag, ioh, off);
return (le32toh(data));
}
static void
_pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int8_t val)
{
ixp425_pci_mem_bs_w_1(tag, ioh, off, val);
}
static void
_pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int16_t val)
{
ixp425_pci_mem_bs_w_2(tag, ioh, off, val);
}
static void
_pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off,
u_int32_t val)
{
ixp425_pci_mem_bs_w_4(tag, ioh, off, htole32(val));
}
#endif /* __ARMEB__ */
/* End of ixp425_pci_space.c */

1104
sys/arm/xscale/ixp425/ixp425_qmgr.c
View File

File diff suppressed because it is too large Load Diff

247
sys/arm/xscale/ixp425/ixp425_qmgr.h
View File

@ -1,247 +0,0 @@
/*-
* Copyright (c) 2006 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*
* $FreeBSD$
*/
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef ARM_XSCALE_IXP425_QMGR_H
#define ARM_XSCALE_IXP425_QMGR_H
#define IX_QMGR_MAX_NUM_QUEUES 64
#define IX_QMGR_MIN_QUEUPP_QID 32
#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
/* Total size of SRAM */
#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
#define IX_QMGR_Q_PRIORITY_0 0
#define IX_QMGR_Q_PRIORITY_1 1
#define IX_QMGR_Q_PRIORITY_2 2
#define IX_QMGR_NUM_PRIORITY_LEVELS 3 /* number of priority levels */
#define IX_QMGR_Q_STATUS_E_BIT_MASK 0x1 /* Empty */
#define IX_QMGR_Q_STATUS_NE_BIT_MASK 0x2 /* Nearly Empty */
#define IX_QMGR_Q_STATUS_NF_BIT_MASK 0x4 /* Nearly Full */
#define IX_QMGR_Q_STATUS_F_BIT_MASK 0x8 /* Full */
#define IX_QMGR_Q_STATUS_UF_BIT_MASK 0x10 /* Underflow */
#define IX_QMGR_Q_STATUS_OF_BIT_MASK 0x20 /* Overflow */
#define IX_QMGR_Q_SOURCE_ID_E 0 /* Q Empty after last read */
#define IX_QMGR_Q_SOURCE_ID_NE 1 /* Q Nearly Empty after last read */
#define IX_QMGR_Q_SOURCE_ID_NF 2 /* Q Nearly Full after last write */
#define IX_QMGR_Q_SOURCE_ID_F 3 /* Q Full after last write */
#define IX_QMGR_Q_SOURCE_ID_NOT_E 4 /* Q !Empty after last write */
#define IX_QMGR_Q_SOURCE_ID_NOT_NE 5 /* Q !Nearly Empty after last write */
#define IX_QMGR_Q_SOURCE_ID_NOT_NF 6 /* Q !Nearly Full after last read */
#define IX_QMGR_Q_SOURCE_ID_NOT_F 7 /* Q !Full after last read */
#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0 /* underflow bit mask */
#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1 /* overflow bit mask */
#define IX_QMGR_QUEACC0_OFFSET 0x0000 /* q 0 access register */
#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
#define IX_QMGR_QUELOWSTAT0_OFFSET 0x400 /* Q status, q's 0-7 */
#define IX_QMGR_QUELOWSTAT1_OFFSET 0x404 /* Q status, q's 8-15 */
#define IX_QMGR_QUELOWSTAT2_OFFSET 0x408 /* Q status, q's 16-23 */
#define IX_QMGR_QUELOWSTAT3_OFFSET 0x40c /* Q status, q's 24-31 */
/* Queue status register Q status bits mask */
#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
/* Size of queue 0-31 status register */
#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8 /* # status/word */
#define IX_QMGR_QUEUOSTAT0_OFFSET 0x410 /* Q UF/OF status, q's 0-15 */
#define IX_QMGR_QUEUOSTAT1_OFFSET 0x414 /* Q UF/OF status, q's 16-31 */
#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16 /* # UF/OF status/word */
#define IX_QMGR_QUEUPPSTAT0_OFFSET 0x418 /* NE status, q's 32-63 */
#define IX_QMGR_QUEUPPSTAT1_OFFSET 0x41c /* F status, q's 32-63 */
#define IX_QMGR_INT0SRCSELREG0_OFFSET 0x420 /* INT src select, q's 0-7 */
#define IX_QMGR_INT0SRCSELREG1_OFFSET 0x424 /* INT src select, q's 8-15 */
#define IX_QMGR_INT0SRCSELREG2_OFFSET 0x428 /* INT src select, q's 16-23 */
#define IX_QMGR_INT0SRCSELREG3_OFFSET 0x42c /* INT src select, q's 24-31 */
#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8 /* # INT src select/word */
#define IX_QMGR_QUEIEREG0_OFFSET 0x430 /* INT enable, q's 0-31 */
#define IX_QMGR_QUEIEREG1_OFFSET 0x434 /* INT enable, q's 32-63 */
#define IX_QMGR_QINTREG0_OFFSET 0x438 /* INT status, q's 0-31 */
#define IX_QMGR_QINTREG1_OFFSET 0x43c /* INT status, q's 32-63 */
#define IX_QMGR_QUECONFIG_BASE_OFFSET 0x2000 /* Q config register, q 0 */
#define IX_QMGR_QUECONFIG_SIZE 0x100 /* total size of Q config regs*/
#define IX_QMGR_QUEBUFFER_SPACE_OFFSET 0x2100 /* start of SRAM */
/* Total bits in a word */
#define BITS_PER_WORD 32
/* Size of queue buffer space */
#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
/*
* This macro will return the address of the access register for the
* queue specified by qId
*/
#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
(((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\
+ IX_QMGR_QUEACC0_OFFSET)
/*
* Bit location of bit-3 of INT0SRCSELREG0 register to enabled
* sticky interrupt register.
*/
#define IX_QMGR_INT0SRCSELREG0_BIT3 3
/*
* These defines are the bit offsets of the various fields of
* the queue configuration register.
*/
#if 0
#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00
#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07
#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E
#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16
#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18
#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A
#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D
#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
#define IX_QMGR_NE_MASK 0x7
#define IX_QMGR_NF_MASK 0x7
#define IX_QMGR_SIZE_MASK 0x3
#define IX_QMGR_ENTRY_SIZE_MASK 0x3
#define IX_QMGR_BADDR_MASK 0x003FC000
#define IX_QMGR_RDPTR_MASK 0x7F
#define IX_QMGR_WRPTR_MASK 0x7F
#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
#else
#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0
#define IX_QMGR_WRPTR_MASK 0x7F
#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 7
#define IX_QMGR_RDPTR_MASK 0x7F
#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 14
#define IX_QMGR_BADDR_MASK 0x3FC000 /* XXX not used */
#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 22
#define IX_QMGR_ENTRY_SIZE_MASK 0x3
#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 24
#define IX_QMGR_SIZE_MASK 0x3
#define IX_QMGR_Q_CONFIG_NE_OFFSET 26
#define IX_QMGR_NE_MASK 0x7
#define IX_QMGR_Q_CONFIG_NF_OFFSET 29
#define IX_QMGR_NF_MASK 0x7
#define IX_QMGR_RDWRPTR_MASK 0x00003FFF
#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF
#endif
#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 64
#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 6
#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
/* Base address of AQM SRAM */
#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
/* Min buffer size used for generating buffer size in QUECONFIG */
#define IX_QMGR_MIN_BUFFER_SIZE 16
/* Reset values of QMgr hardware registers */
#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333
#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000
#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF
#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000
#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000
#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF
#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000
#define IX_QMGR_QUELOWSTAT_BITS_PER_Q \
(BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
(((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET)
#define IX_QMGR_ENTRY1_OFFSET 0
#define IX_QMGR_ENTRY2_OFFSET 1
#define IX_QMGR_ENTRY4_OFFSET 3
typedef void qconfig_hand_t(int, void *);
int ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel,
qconfig_hand_t *cb, void *cbarg);
int ixpqmgr_qwrite(int qId, uint32_t entry);
int ixpqmgr_qread(int qId, uint32_t *entry);
int ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p);
uint32_t ixpqmgr_getqstatus(int qId);
uint32_t ixpqmgr_getqconfig(int qId);
void ixpqmgr_notify_enable(int qId, int srcSel);
void ixpqmgr_notify_disable(int qId);
void ixpqmgr_dump(void);
#endif /* ARM_XSCALE_IXP425_QMGR_H */

125
sys/arm/xscale/ixp425/ixp425_space.c
View File

@ -1,125 +0,0 @@
/* $NetBSD: ixp425_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* bus_space I/O functions for ixp425
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
/* Proto types for all the bus_space structure functions */
bs_protos(generic);
struct bus_space ixp425_bs_tag = {
/* cookie */
.bs_privdata = (void *) 0,
/* mapping/unmapping */
.bs_map = generic_bs_map,
.bs_unmap = generic_bs_unmap,
.bs_subregion = generic_bs_subregion,
/* allocation/deallocation */
.bs_alloc = generic_bs_alloc,
.bs_free = generic_bs_free,
/* barrier */
.bs_barrier = generic_bs_barrier,
/* read (single) */
.bs_r_1 = generic_bs_r_1,
.bs_r_2 = generic_bs_r_2,
.bs_r_4 = generic_bs_r_4,
.bs_r_8 = NULL,
/* read multiple */
.bs_rm_1 = generic_bs_rm_1,
.bs_rm_2 = generic_bs_rm_2,
.bs_rm_4 = generic_bs_rm_4,
.bs_rm_8 = NULL,
/* read region */
.bs_rr_1 = generic_bs_rr_1,
.bs_rr_2 = generic_bs_rr_2,
.bs_rr_4 = generic_bs_rr_4,
.bs_rr_8 = NULL,
/* write (single) */
.bs_w_1 = generic_bs_w_1,
.bs_w_2 = generic_bs_w_2,
.bs_w_4 = generic_bs_w_4,
.bs_w_8 = NULL,
/* write multiple */
.bs_wm_1 = generic_bs_wm_1,
.bs_wm_2 = generic_bs_wm_2,
.bs_wm_4 = generic_bs_wm_4,
.bs_wm_8 = NULL,
/* write region */
.bs_wr_1 = generic_bs_wr_1,
.bs_wr_2 = generic_bs_wr_2,
.bs_wr_4 = generic_bs_wr_4,
.bs_wr_8 = NULL,
/* set multiple */
/* XXX not implemented */
/* set region */
.bs_sr_1 = NULL,
.bs_sr_2 = generic_bs_sr_2,
.bs_sr_4 = generic_bs_sr_4,
.bs_sr_8 = NULL,
/* copy */
.bs_c_1 = NULL,
.bs_c_2 = generic_bs_c_2,
.bs_c_4 = NULL,
.bs_c_8 = NULL,
};

266
sys/arm/xscale/ixp425/ixp425_timer.c
View File

@ -1,266 +0,0 @@
/* $NetBSD: ixp425_timer.c,v 1.15 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/time.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/timetc.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <machine/resource.h>
#include <machine/intr.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
static uint32_t counts_per_hz;
/* callback functions for intr_functions */
int ixpclk_intr(void *);
struct ixpclk_softc {
device_t sc_dev;
bus_addr_t sc_baseaddr;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_ioh;
};
static unsigned ixp425_timer_get_timecount(struct timecounter *tc);
#ifndef IXP425_CLOCK_FREQ
#define COUNTS_PER_SEC 66666600 /* 66MHz */
#else
#define COUNTS_PER_SEC IXP425_CLOCK_FREQ
#endif
#define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1)
static struct ixpclk_softc *ixpclk_sc = NULL;
#define GET_TS_VALUE(sc) (*(volatile u_int32_t *) \
(IXP425_TIMER_VBASE + IXP425_OST_TS))
static struct timecounter ixp425_timer_timecounter = {
ixp425_timer_get_timecount, /* get_timecount */
NULL, /* no poll_pps */
~0u, /* counter_mask */
COUNTS_PER_SEC, /* frequency */
"IXP4XX Timer", /* name */
1000, /* quality */
};
static int
ixpclk_probe(device_t dev)
{
device_set_desc(dev, "IXP4XX Timer");
return (0);
}
static int
ixpclk_attach(device_t dev)
{
struct ixpclk_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
ixpclk_sc = sc;
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_baseaddr = IXP425_TIMER_HWBASE;
if (bus_space_map(sc->sc_iot, sc->sc_baseaddr, 8, 0,
&sc->sc_ioh))
panic("%s: Cannot map registers", device_get_name(dev));
return (0);
}
static device_method_t ixpclk_methods[] = {
DEVMETHOD(device_probe, ixpclk_probe),
DEVMETHOD(device_attach, ixpclk_attach),
{0, 0},
};
static driver_t ixpclk_driver = {
"ixpclk",
ixpclk_methods,
sizeof(struct ixpclk_softc),
};
static devclass_t ixpclk_devclass;
DRIVER_MODULE(ixpclk, ixp, ixpclk_driver, ixpclk_devclass, 0, 0);
static unsigned
ixp425_timer_get_timecount(struct timecounter *tc)
{
uint32_t ret;
ret = GET_TS_VALUE(sc);
return (ret);
}
/*
* cpu_initclocks:
*
* Initialize the clock and get them going.
*/
void
cpu_initclocks(void)
{
struct ixpclk_softc* sc = ixpclk_sc;
struct resource *irq;
device_t dev = sc->sc_dev;
u_int oldirqstate;
int rid = 0;
void *ihl;
if (hz < 50 || COUNTS_PER_SEC % hz) {
printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
hz = 100;
}
tick = 1000000 / hz; /* number of microseconds between interrupts */
/*
* We only have one timer available; stathz and profhz are
* always left as 0 (the upper-layer clock code deals with
* this situation).
*/
if (stathz != 0)
printf("Cannot get %d Hz statclock\n", stathz);
stathz = 0;
if (profhz != 0)
printf("Cannot get %d Hz profclock\n", profhz);
profhz = 0;
/* Report the clock frequency. */
oldirqstate = disable_interrupts(PSR_I);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0,
IXP425_INT_TMR0, 1, RF_ACTIVE);
if (!irq)
panic("Unable to setup the clock irq handler.\n");
else
bus_setup_intr(dev, irq, INTR_TYPE_CLK, ixpclk_intr, NULL,
NULL, &ihl);
/* Set up the new clock parameters. */
/* clear interrupt */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT |
OST_TIM1_INT | OST_TIM0_INT);
counts_per_hz = COUNTS_PER_SEC / hz;
/* reload value & Timer enable */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD,
(counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN);
tc_init(&ixp425_timer_timecounter);
restore_interrupts(oldirqstate);
rid = 0;
}
/*
* DELAY:
*
* Delay for at least N microseconds.
*/
void
DELAY(int n)
{
u_int32_t first, last;
int usecs;
if (n == 0)
return;
TSENTER();
/*
* Clamp the timeout at a maximum value (about 32 seconds with
* a 66MHz clock). *Nobody* should be delay()ing for anywhere
* near that length of time and if they are, they should be hung
* out to dry.
*/
if (n >= (0x80000000U / COUNTS_PER_USEC))
usecs = (0x80000000U / COUNTS_PER_USEC) - 1;
else
usecs = n * COUNTS_PER_USEC;
/* Note: Timestamp timer counts *up*, unlike the other timers */
first = GET_TS_VALUE();
while (usecs > 0) {
last = GET_TS_VALUE();
usecs -= (int)(last - first);
first = last;
}
TSEXIT();
}
/*
* ixpclk_intr:
*
* Handle the hardclock interrupt.
*/
int
ixpclk_intr(void *arg)
{
struct ixpclk_softc* sc = ixpclk_sc;
struct trapframe *frame = arg;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS,
OST_TIM0_INT);
hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
return (FILTER_HANDLED);
}
void
cpu_startprofclock(void)
{
}
void
cpu_stopprofclock(void)
{
}

117
sys/arm/xscale/ixp425/ixp425_wdog.c
View File

@ -1,117 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* IXP4XX Watchdog Timer Support.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/time.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/watchdog.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/intr.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
struct ixpwdog_softc {
device_t sc_dev;
};
static __inline uint32_t
RD4(struct ixpwdog_softc *sc, bus_size_t off)
{
return bus_space_read_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off);
}
static __inline void
WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val)
{
bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off, val);
}
static void
ixp425_watchdog(void *arg, u_int cmd, int *error)
{
struct ixpwdog_softc *sc = arg;
u_int u = cmd & WD_INTERVAL;
WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK);
if (4 <= u && u <= 35) {
WR4(sc, IXP425_OST_WDOG_ENAB, 0);
/* approximate 66.66MHz cycles */
WR4(sc, IXP425_OST_WDOG, 2<<(u - 4));
/* NB: reset on timer expiration */
WR4(sc, IXP425_OST_WDOG_ENAB,
OST_WDOG_ENAB_CNT_ENA | OST_WDOG_ENAB_RST_ENA);
*error = 0;
} else {
/* disable watchdog */
WR4(sc, IXP425_OST_WDOG_ENAB, 0);
}
WR4(sc, IXP425_OST_WDOG_KEY, 0);
}
static int
ixpwdog_probe(device_t dev)
{
device_set_desc(dev, "IXP4XX Watchdog Timer");
return (0);
}
static int
ixpwdog_attach(device_t dev)
{
struct ixpwdog_softc *sc = device_get_softc(dev);
sc->sc_dev = dev;
EVENTHANDLER_REGISTER(watchdog_list, ixp425_watchdog, sc, 0);
return (0);
}
static device_method_t ixpwdog_methods[] = {
DEVMETHOD(device_probe, ixpwdog_probe),
DEVMETHOD(device_attach, ixpwdog_attach),
{0, 0},
};
static driver_t ixpwdog_driver = {
"ixpwdog",
ixpwdog_methods,
sizeof(struct ixpwdog_softc),
};
static devclass_t ixpwdog_devclass;
DRIVER_MODULE(ixpwdog, ixp, ixpwdog_driver, ixpwdog_devclass, 0, 0);

710
sys/arm/xscale/ixp425/ixp425reg.h
View File

@ -1,710 +0,0 @@
/* $NetBSD: ixp425reg.h,v 1.21 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IXP425REG_H_
#define _IXP425REG_H_
/*
* Physical memory map for the Intel IXP425
*/
/*
* CC00 00FF ---------------------------
* SDRAM Configuration Registers
* CC00 0000 ---------------------------
*
* C800 BFFF ---------------------------
* System and Peripheral Registers
* C800 0000 ---------------------------
* Expansion Bus Configuration Registers
* C400 0000 ---------------------------
* PCI Configuration and Status Registers
* C000 0000 ---------------------------
*
* 6400 0000 ---------------------------
* Queue manager
* 6000 0000 ---------------------------
* Expansion Bus Data
* 5000 0000 ---------------------------
* PCI Data
* 4800 0000 ---------------------------
*
* 4000 0000 ---------------------------
* SDRAM
* 0000 0000 ---------------------------
*/
/*
* Virtual memory map for the Intel IXP425/IXP435 integrated devices
*/
/*
* FFFF FFFF ---------------------------
*
* Global cache clean area
* FF00 0000 ---------------------------
*
* FE00 0000 ---------------------------
* 16M CFI Flash (on ext bus)
* FD00 0000 ---------------------------
*
* FC00 0000 ---------------------------
* PCI Data (memory space)
* F800 0000 --------------------------- IXP425_PCI_MEM_VBASE
*
* F020 1000 ---------------------------
* SDRAM/DDR Memory Controller
* F020 0000 --------------------------- IXP425_MCU_VBASE
*
* F001 F000 RS485 (Cambria) CAMBRIA_RS485_VBASE
* F001 E000 GPS (Cambria) CAMBRIA_GPS_VBASE
* F001 D000 EHCI USB 2 (IXP435) IXP435_USB2_VBASE
* F001 C000 EHCI USB 1 (IXP435) IXP435_USB1_VBASE
* Queue manager
* F001 8000 --------------------------- IXP425_QMGR_VBASE
* PCI Configuration and Status
* F001 7000 --------------------------- IXP425_PCI_VBASE
*
* (NB: gap for future addition of EXP CS5-7)
* F001 4000 Expansion Bus Chip Select 4
* F001 3000 Expansion Bus Chip Select 3
* F001 2000 Expansion Bus Chip Select 2
* F001 1000 Expansion Bus Chip Select 1
* Expansion Bus Configuration
* F001 0000 --------------------------- IXP425_EXP_VBASE
*
* F000 C000 MAC-A (IXP435)
* F000 B000 USB (option on IXP425)
* F000 A000 MAC-B (IXP425) | MAC-C (IXP435)
* F000 9000 MAC-A (IXP425)
* F000 8000 NPE-C
* F000 7000 NPE-B (IXP425)
* F000 6000 NPE-A
* F000 5000 Timers
* F000 4000 GPIO Controller
* F000 3000 Interrupt Controller
* F000 2000 Performance Monitor Controller (PMC)
* F000 1000 UART 1 (IXP425)
* F000 0000 UART 0
* F000 0000 --------------------------- IXP425_IO_VBASE
*
* 0000 0000 ---------------------------
*
*/
/* Physical/Virtual address for I/O space */
#define IXP425_IO_VBASE 0xf0000000UL
#define IXP425_IO_HWBASE 0xc8000000UL
#define IXP425_IO_SIZE 0x00010000UL
/* Physical/Virtual addresss offsets */
#define IXP425_UART0_OFFSET 0x00000000UL
#define IXP425_UART1_OFFSET 0x00001000UL
#define IXP425_PMC_OFFSET 0x00002000UL
#define IXP425_INTR_OFFSET 0x00003000UL
#define IXP425_GPIO_OFFSET 0x00004000UL
#define IXP425_TIMER_OFFSET 0x00005000UL
#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */
#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */
#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */
#define IXP425_MAC_B_OFFSET 0x00009000UL /* Ethernet MAC on NPE-B */
#define IXP425_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE-C */
#define IXP425_USB_OFFSET 0x0000b000UL
#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE-A */
#define IXP425_REG_SIZE 0x1000
/*
* UART
* UART0 0xc8000000
* UART1 0xc8001000
*
*/
/* I/O space */
#define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET)
#define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET)
#define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET)
/* 0xf0000000 */
#define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET)
/* 0xf0001000 */
#define IXP425_UART_FREQ 14745600
#define IXP425_UART_IER 0x01 /* interrupt enable register */
#define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */
#define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */
/*#define IXP4XX_COM_NPORTS 8*/
/*
* Timers
*/
#define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET)
#define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET)
#define IXP425_OST_TS 0x0000
#define IXP425_OST_TIM0 0x0004
#define IXP425_OST_TIM1 0x000C
#define IXP425_OST_TIM0_RELOAD 0x0008
#define IXP425_OST_TIM1_RELOAD 0x0010
#define TIMERRELOAD_MASK 0xFFFFFFFC
#define OST_ONESHOT_EN (1U << 1)
#define OST_TIMER_EN (1U << 0)
#define IXP425_OST_STATUS 0x0020
#define OST_WARM_RESET (1U << 4)
#define OST_WDOG_INT (1U << 3)
#define OST_TS_INT (1U << 2)
#define OST_TIM1_INT (1U << 1)
#define OST_TIM0_INT (1U << 0)
#define IXP425_OST_WDOG 0x0014
#define IXP425_OST_WDOG_ENAB 0x0018
#define IXP425_OST_WDOG_KEY 0x001c
#define OST_WDOG_KEY_MAJICK 0x482e
#define OST_WDOG_ENAB_RST_ENA (1u << 0)
#define OST_WDOG_ENAB_INT_ENA (1u << 1)
#define OST_WDOG_ENAB_CNT_ENA (1u << 2)
/*
* Interrupt Controller Unit.
* PA 0xc8003000
*/
#define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET
#define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET
/* 0xf0003000 */
#define IXP425_IRQ_SIZE 0x00000020UL
#define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00)
#define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04)
#define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08)
#define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C)
#define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10)
#define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14)
#define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18)
#define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C)
#define IXP425_INT_SW1 31 /* SW Interrupt 1 */
#define IXP425_INT_SW0 30 /* SW Interrupt 0 */
#define IXP425_INT_GPIO_12 29 /* GPIO 12 */
#define IXP425_INT_GPIO_11 28 /* GPIO 11 */
#define IXP425_INT_GPIO_10 27 /* GPIO 11 */
#define IXP425_INT_GPIO_9 26 /* GPIO 9 */
#define IXP425_INT_GPIO_8 25 /* GPIO 8 */
#define IXP425_INT_GPIO_7 24 /* GPIO 7 */
#define IXP425_INT_GPIO_6 23 /* GPIO 6 */
#define IXP425_INT_GPIO_5 22 /* GPIO 5 */
#define IXP425_INT_GPIO_4 21 /* GPIO 4 */
#define IXP425_INT_GPIO_3 20 /* GPIO 3 */
#define IXP425_INT_GPIO_2 19 /* GPIO 2 */
#define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */
#define IXP425_INT_AHB_PMU 17 /* AHB PMU */
#define IXP425_INT_WDOG 16 /* Watchdog Timer */
#define IXP425_INT_UART0 15 /* HighSpeed UART */
#define IXP425_INT_STAMP 14 /* Timestamp Timer */
#define IXP425_INT_UART1 13 /* Console UART */
#define IXP425_INT_USB 12 /* USB */
#define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */
#define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */
#define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */
#define IXP425_INT_PCIINT 8 /* PCI Interrupt */
#define IXP425_INT_GPIO_1 7 /* GPIO 1 */
#define IXP425_INT_GPIO_0 6 /* GPIO 0 */
#define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */
#define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */
#define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */
#define IXP425_INT_NPE_C 2 /* NPE C */
#define IXP425_INT_NPE_B 1 /* NPE B */
#define IXP425_INT_NPE_A 0 /* NPE A */
/* NB: IXP435 has an additional 32 IRQ's */
#define IXP435_INT_STATUS2 (IXP425_IRQ_VBASE + 0x20)
#define IXP435_INT_ENABLE2 (IXP425_IRQ_VBASE + 0x24)
#define IXP435_INT_SELECT2 (IXP425_IRQ_VBASE + 0x28)
#define IXP435_IRQ_STATUS2 (IXP425_IRQ_VBASE + 0x2C)
#define IXP435_FIQ_STATUS2 (IXP425_IRQ_VBASE + 0x30)
#define IXP435_INT_USB0 32 /* USB Host 2.0 Host 0 */
#define IXP435_INT_USB1 33 /* USB Host 2.0 Host 1 */
#define IXP435_INT_QMGR_PER 60 /* Queue manager parity error */
#define IXP435_INT_ECC 61 /* Single or multi-bit ECC error */
/*
* software interrupt
*/
#define IXP425_INT_bit31 31
#define IXP425_INT_bit30 30
#define IXP425_INT_bit14 14
#define IXP425_INT_bit11 11
#define IXP425_INT_HWMASK (0xffffffff & \
~((1 << IXP425_INT_bit31) | \
(1 << IXP425_INT_bit30) | \
(1 << IXP425_INT_bit14) | \
(1 << IXP425_INT_bit11)))
#define IXP425_INT_GPIOMASK (0x3ff800c0u)
#define IXP435_INT_HWMASK ((1 << (IXP435_INT_USB0 - 32)) | \
(1 << (IXP435_INT_USB1 - 32)) | \
(1 << (IXP435_INT_QMGR_PER - 32)) | \
(1 << (IXP435_INT_ECC - 32)))
/*
* GPIO
*/
#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET
#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET
/* 0xf0004000 */
#define IXP425_GPIO_SIZE 0x00000020UL
#define IXP425_GPIO_GPOUTR 0x00
#define IXP425_GPIO_GPOER 0x04
#define IXP425_GPIO_GPINR 0x08
#define IXP425_GPIO_GPISR 0x0c
#define IXP425_GPIO_GPIT1R 0x10
#define IXP425_GPIO_GPIT2R 0x14
#define IXP425_GPIO_GPCLKR 0x18
# define GPCLKR_MUX14 (1U << 8)
# define GPCLKR_CLK0TC_SHIFT 4
# define GPCLKR_CLK0DC_SHIFT 0
/* GPIO Output */
#define GPOUT_ON 0x1
#define GPOUT_OFF 0x0
/* GPIO direction */
#define GPOER_INPUT 0x1
#define GPOER_OUTPUT 0x0
/* GPIO Type bits */
#define GPIO_TYPE_ACT_HIGH 0x0
#define GPIO_TYPE_ACT_LOW 0x1
#define GPIO_TYPE_EDG_RISING 0x2
#define GPIO_TYPE_EDG_FALLING 0x3
#define GPIO_TYPE_TRANSITIONAL 0x4
#define GPIO_TYPE_MASK 0x7
#define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3))
#define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R)
#define IXP4XX_GPIO_PINS 16
/*
* Expansion Bus Configuration Space.
*/
#define IXP425_EXP_HWBASE 0xc4000000UL
#define IXP425_EXP_VBASE 0xf0010000UL
#define IXP425_EXP_SIZE 0x1000
/* offset */
#define EXP_TIMING_CS0_OFFSET 0x0000
#define EXP_TIMING_CS1_OFFSET 0x0004
#define EXP_TIMING_CS2_OFFSET 0x0008
#define EXP_TIMING_CS3_OFFSET 0x000c
#define EXP_TIMING_CS4_OFFSET 0x0010
#define EXP_TIMING_CS5_OFFSET 0x0014
#define EXP_TIMING_CS6_OFFSET 0x0018
#define EXP_TIMING_CS7_OFFSET 0x001c
#define EXP_CNFG0_OFFSET 0x0020
#define EXP_CNFG1_OFFSET 0x0024
#define EXP_FCTRL_OFFSET 0x0028
#define IXP425_EXP_RECOVERY_SHIFT 16
#define IXP425_EXP_HOLD_SHIFT 20
#define IXP425_EXP_STROBE_SHIFT 22
#define IXP425_EXP_SETUP_SHIFT 26
#define IXP425_EXP_ADDR_SHIFT 28
#define IXP425_EXP_CS_EN (1U << 31)
#define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT)
#define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT)
#define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT)
#define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT)
#define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT)
/* EXP_CSn bits */
#define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */
#define EXP_WR_EN 0x00000002 /* ena writes to CS region */
/* bit 2 is reserved */
#define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */
#define EXP_MUX_EN 0x00000010 /* multiplexed address/data */
#define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */
#define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */
#define EXP_CNFG 0x00003c00 /* device config size */
#define EXP_SZ_512 (0 << 10)
#define EXP_SZ_1K (1 << 10)
#define EXP_SZ_2K (2 << 10)
#define EXP_SZ_4K (3 << 10)
#define EXP_SZ_8K (4 << 10)
#define EXP_SZ_16K (5 << 10)
#define EXP_SZ_32K (6 << 10)
#define EXP_SZ_64K (7 << 10)
#define EXP_SZ_128K (8 << 10)
#define EXP_SZ_256K (9 << 10)
#define EXP_SZ_512K (10 << 10)
#define EXP_SZ_1M (11 << 10)
#define EXP_SZ_2M (12 << 10)
#define EXP_SZ_4M (13 << 10)
#define EXP_SZ_8M (14 << 10)
#define EXP_SZ_16M (15 << 10)
#define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */
#define EXP_CYC_INTEL (0 << 14)
#define EXP_CYC_MOTO (1 << 14)
#define EXP_CYC_HPI (2 << 14)
#define EXP_T5 0x000f0000 /* recovery timing */
#define EXP_T4 0x00300000 /* hold timing */
#define EXP_T3 0x03c00000 /* strobe timing */
#define EXP_T2 0x0c000000 /* setup/chip select timing */
#define EXP_T1 0x30000000 /* address timing */
/* bit 30 is reserved */
#define EXP_CS_EN 0x80000000 /* chip select enabled */
/* EXP_CNFG0 bits */
#define EXP_CNFG0_8BIT (1 << 0)
#define EXP_CNFG0_PCI_HOST (1 << 1)
#define EXP_CNFG0_PCI_ARB (1 << 2)
#define EXP_CNFG0_PCI_66MHZ (1 << 4)
#define EXP_CNFG0_MEM_MAP (1U << 31)
/* EXP_CNFG1 bits */
#define EXP_CNFG1_SW_INT0 (1 << 0)
#define EXP_CNFG1_SW_INT1 (1 << 1)
#define EXP_FCTRL_RCOMP (1<<0)
#define EXP_FCTRL_USB_DEVICE (1<<1)
#define EXP_FCTRL_HASH (1<<2)
#define EXP_FCTRL_AES (1<<3)
#define EXP_FCTRL_DES (1<<4)
#define EXP_FCTRL_HDLC (1<<5)
#define EXP_FCTRL_AAL (1<<6)
#define EXP_FCTRL_HSS (1<<7)
#define EXP_FCTRL_UTOPIA (1<<8)
#define EXP_FCTRL_ETH0 (1<<9)
#define EXP_FCTRL_ETH1 (1<<10)
#define EXP_FCTRL_NPEA (1<<11) /* reset */
#define EXP_FCTRL_NPEB (1<<12) /* reset */
#define EXP_FCTRL_NPEC (1<<13) /* reset */
#define EXP_FCTRL_PCI (1<<14)
#define EXP_FCTRL_ECC_TIMESYNC (1<<15)
#define EXP_FCTRL_UTOPIA_PHY (3<<16) /* PHY limit */
#define EXP_FCTRL_USB_HOST (1<<18)
#define EXP_FCTRL_NPEA_ETH (1<<19)
#define EXP_FCTRL_NPEB_ETH (1<<20)
#define EXP_FCTRL_RSA (1<<21)
#define EXP_FCTRL_MAXFREQ (3<<22) /* XScale frequency */
#define EXP_FCTRL_RESVD (0xff<<24)
#define EXP_FCTRL_IXP46X_ONLY \
(EXP_FCTRL_ECC_TIMESYNC | EXP_FCTRL_USB_HOST | EXP_FCTRL_NPEA_ETH | \
EXP_FCTRL_NPEB_ETH | EXP_FCTRL_RSA | EXP_FCTRL_MAXFREQ)
#define EXP_FCTRL_BITS \
"\20\1RCOMP\2USB\3HASH\4AES\5DES\6HDLC\7AAL\10HSS\11UTOPIA\12ETH0" \
"\13ETH1\17PCI\20ECC\23USB_HOST\24NPEA_ETH\25NPEB_ETH\26RSA"
/*
* PCI
*/
#define IXP425_PCI_HWBASE 0xc0000000
#define IXP425_PCI_VBASE 0xf0017000UL
#define IXP425_PCI_SIZE 0x1000
#define IXP425_AHB_OFFSET 0x00000000UL /* AHB bus */
/*
* Mapping registers of IXP425 PCI Configuration
*/
/* PCI_ID_REG 0x00 */
/* PCI_COMMAND_STATUS_REG 0x04 */
/* PCI_CLASS_REG 0x08 */
/* PCI_BHLC_REG 0x0c */
#define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */
#define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */
#define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */
#define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */
#define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */
#define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */
/* PCI_SUBSYS_ID_REG 0x2c */
/* PCI_INTERRUPT_REG 0x3c */
#define PCI_RTOTTO 0x40
/* PCI Controller CSR Base Address */
#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE
/* PCI Memory Space */
#define IXP425_PCI_MEM_HWBASE 0x48000000UL
#define IXP425_PCI_MEM_VBASE 0xf8000000UL
#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */
/* PCI I/O Space */
#define IXP425_PCI_IO_HWBASE 0x00000000UL
#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */
/* PCI Controller Configuration Offset */
#define PCI_NP_AD 0x00
#define PCI_NP_CBE 0x04
# define NP_CBE_SHIFT 4
#define PCI_NP_WDATA 0x08
#define PCI_NP_RDATA 0x0c
#define PCI_CRP_AD_CBE 0x10
#define PCI_CRP_AD_WDATA 0x14
#define PCI_CRP_AD_RDATA 0x18
#define PCI_CSR 0x1c
# define CSR_PRST (1U << 16)
# define CSR_IC (1U << 15)
# define CSR_ABE (1U << 4)
# define CSR_PDS (1U << 3)
# define CSR_ADS (1U << 2)
# define CSR_HOST (1U << 0)
#define PCI_ISR 0x20
# define ISR_AHBE (1U << 3)
# define ISR_PPE (1U << 2)
# define ISR_PFE (1U << 1)
# define ISR_PSE (1U << 0)
#define PCI_INTEN 0x24
#define PCI_DMACTRL 0x28
#define PCI_AHBMEMBASE 0x2c
#define PCI_AHBIOBASE 0x30
#define PCI_PCIMEMBASE 0x34
#define PCI_AHBDOORBELL 0x38
#define PCI_PCIDOORBELL 0x3c
#define PCI_ATPDMA0_AHBADDR 0x40
#define PCI_ATPDMA0_PCIADDR 0x44
#define PCI_ATPDMA0_LENGTH 0x48
#define PCI_ATPDMA1_AHBADDR 0x4c
#define PCI_ATPDMA1_PCIADDR 0x50
#define PCI_ATPDMA1_LENGTH 0x54
#define PCI_PTADMA0_AHBADDR 0x58
#define PCI_PTADMA0_PCIADDR 0x5c
#define PCI_PTADMA0_LENGTH 0x60
#define PCI_PTADMA1_AHBADDR 0x64
#define PCI_PTADMA1_PCIADDR 0x68
#define PCI_PTADMA1_LENGTH 0x6c
/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */
#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/
#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/
#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */
#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */
#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */
#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */
#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */
#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */
/* PCI byte enables */
#define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0)
#define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0)
#define BE_32BIT(a) 0x00
/* PCI byte selects */
#define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8)))
#define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8)))
#define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8))
#define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8))
/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */
#define COMMAND_CRP_READ 0x00
#define COMMAND_CRP_WRITE (1U << 16)
/*
* SDRAM Configuration Register
*/
#define IXP425_MCU_HWBASE 0xcc000000UL
#define IXP425_MCU_VBASE 0xf0200000UL
#define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */
#define MCU_SDR_CONFIG 0x00
#define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7)
#define MCU_SDR_CONFIG_64MBIT (1u << 5)
#define MCU_SDR_REFRESH 0x04
#define MCU_SDR_IR 0x08
/*
* IXP435 DDR MCU Registers
*/
#define IXP435_MCU_HWBASE 0xcc00e500UL
#define MCU_DDR_SDIR 0x00 /* DDR SDAM Initialization Reg*/
#define MCU_DDR_SDCR0 0x04 /* DDR SDRAM Control Reg 0 */
#define MCU_DDR_SDCR1 0x08 /* DDR SDRAM Control Reg 1 */
#define MCU_DDR_SDBR 0x0c /* SDRAM Base Register */
#define MCU_DDR_SBR0 0x10 /* SDRAM Boundary Register 0 */
#define MCU_DDR_SBR1 0x14 /* SDRAM Boundary Register 1 */
#define MCU_DDR_ECCR 0x1c /* ECC Control Register */
#define MCU_DDR_ELOG0 0x20 /* ECC Log Register 0 */
#define MCU_DDR_ELOG1 0x24 /* ECC Log Register 1 */
#define MCU_DDR_ECAR0 0x28 /* ECC Address Register 0 */
#define MCU_DDR_ECAR1 0x2c /* ECC Address Register 1 */
#define MCU_DDR_ECTST 0x30 /* ECC Test Register */
#define MCU_DDR_MCISR 0x34 /* MC Interrupt Status Reg */
#define MCU_DDR_MPTCR 0x3c /* MC Port Transaction Cnt Reg*/
#define MCU_DDR_RFR 0x48 /* Refresh Frequency Register */
#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */
/* NB: RCVDLY at 0x1050 and LEGOVERIDE at 0x1074 */
/*
* Performance Monitoring Unit (CP14)
*
* CP14.0.1 Performance Monitor Control Register(PMNC)
* CP14.1.1 Clock Counter(CCNT)
* CP14.4.1 Interrupt Enable Register(INTEN)
* CP14.5.1 Overflow Flag Register(FLAG)
* CP14.8.1 Event Selection Register(EVTSEL)
* CP14.0.2 Performance Counter Register 0(PMN0)
* CP14.1.2 Performance Counter Register 0(PMN1)
* CP14.2.2 Performance Counter Register 0(PMN2)
* CP14.3.2 Performance Counter Register 0(PMN3)
*/
#define PMNC_E 0x00000001 /* enable all counters */
#define PMNC_P 0x00000002 /* reset all PMNs to 0 */
#define PMNC_C 0x00000004 /* clock counter reset */
#define PMNC_D 0x00000008 /* clock counter / 64 */
#define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */
#define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */
#define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */
#define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */
#define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */
#define FLAG_CC_IF 0x00000001 /* clock counter overflow */
#define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */
#define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */
#define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */
#define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */
#define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */
#define PMNC_EVCNT0_SHIFT 0
#define PMNC_EVCNT1_SHIFT 8
#define PMNC_EVCNT2_SHIFT 16
#define PMNC_EVCNT3_SHIFT 24
/*
* Queue Manager
*/
#define IXP425_QMGR_HWBASE 0x60000000UL
#define IXP425_QMGR_VBASE 0xf0018000UL
#define IXP425_QMGR_SIZE 0x4000
/*
* Network Processing Engines (NPE's) and associated Ethernet MAC's.
*/
#define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET)
#define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET)
#define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */
#define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET)
#define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET)
#define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */
#define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET)
#define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET)
#define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */
#define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET)
#define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET)
#define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */
#define IXP425_MAC_C_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_C_OFFSET)
#define IXP425_MAC_C_VBASE (IXP425_IO_VBASE + IXP425_MAC_C_OFFSET)
#define IXP425_MAC_C_SIZE 0x1000 /* Actually only 256 bytes */
#define IXP435_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_A_OFFSET)
#define IXP435_MAC_A_VBASE (IXP425_IO_VBASE + IXP435_MAC_A_OFFSET)
#define IXP435_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */
/*
* Expansion Bus Data Space.
*/
#define IXP425_EXP_BUS_HWBASE 0x50000000UL
#define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */
#define IXP425_EXP_BUS_CSx_HWBASE(i) \
(IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE)
#define IXP425_EXP_BUS_CSx_SIZE 0x1000
#define IXP425_EXP_BUS_CSx_VBASE(i) \
(0xF0011000UL + (((i)-1)*IXP425_EXP_BUS_CSx_SIZE))
/* NB: CS0 is special; it maps flash */
#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0)
#define IXP425_EXP_BUS_CS0_VBASE 0xFD000000UL
#ifndef IXP4XX_FLASH_SIZE
#define IXP425_EXP_BUS_CS0_SIZE 0x01000000 /* NB: 16M */
#else
#define IXP425_EXP_BUS_CS0_SIZE IXP4XX_FLASH_SIZE
#endif
#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1)
#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1)
#define IXP425_EXP_BUS_CS1_SIZE IXP425_EXP_BUS_CSx_SIZE
#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2)
#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2)
#define IXP425_EXP_BUS_CS2_SIZE IXP425_EXP_BUS_CSx_SIZE
#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3)
#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3)
#define IXP425_EXP_BUS_CS3_SIZE IXP425_EXP_BUS_CSx_SIZE
#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4)
#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4)
#define IXP425_EXP_BUS_CS4_SIZE IXP425_EXP_BUS_CSx_SIZE
/* NB: not mapped (yet) */
#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5)
#define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6)
#define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7)
/*
* IXP435/Gateworks Cambria
*/
#define IXP435_USB1_HWBASE 0xCD000000UL /* USB host controller 1 */
#define IXP435_USB1_VBASE 0xF001C000UL
#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */
#define IXP435_USB2_HWBASE 0xCE000000UL /* USB host controller 2 */
#define IXP435_USB2_VBASE 0xF001D000UL
#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */
#define CAMBRIA_GPS_HWBASE 0x53FC0000UL /* optional GPS Serial Port */
#define CAMBRIA_GPS_VBASE 0xF001E000UL
#define CAMBRIA_GPS_SIZE 0x1000
#define CAMBRIA_RS485_HWBASE 0x53F80000UL /* optional RS485 Serial Port */
#define CAMBRIA_RS485_VBASE 0xF001F000UL
#define CAMBRIA_RS485_SIZE 0x1000
/* NB: these are mapped on the fly, so no fixed virtual addresses */
#define CAMBRIA_OCTAL_LED_HWBASE 0x53F40000UL /* Octal Status LED Latch */
#define CAMBRIA_OCTAL_LED_SIZE 0x1000
#define CAMBRIA_CFSEL1_HWBASE 0x53E40000UL /* Compact Flash Socket Sel 0 */
#define CAMBRIA_CFSEL1_SIZE 0x40000
#define CAMBRIA_CFSEL0_HWBASE 0x53E00000UL /* Compact Flash Socket Sel 1 */
#define CAMBRIA_CFSEL0_SIZE 0x40000
#endif /* _IXP425REG_H_ */

124
sys/arm/xscale/ixp425/ixp425var.h
View File

@ -1,124 +0,0 @@
/* $NetBSD: ixp425var.h,v 1.12 2009/10/21 14:15:51 rmind Exp $ */
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 2003
* Ichiro FUKUHARA <ichiro@ichiro.org>.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _IXP425VAR_H_
#define _IXP425VAR_H_
#include <sys/conf.h>
#include <sys/queue.h>
#include <machine/bus.h>
#include <sys/rman.h>
/* NB: cputype is setup by set_cpufuncs */
#define cpu_is_ixp42x() (cputype == CPU_ID_IXP425)
#define cpu_is_ixp43x() (cputype == CPU_ID_IXP435)
#define cpu_is_ixp46x() (cputype == CPU_ID_IXP465)
struct ixp425_softc {
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
bus_space_handle_t sc_exp_ioh;
u_int32_t sc_intrmask;
struct rman sc_irq_rman;
struct rman sc_mem_rman;
bus_dma_tag_t sc_dmat;
};
void ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type);
struct ixppcib_softc {
device_t sc_dev;
u_int sc_bus;
struct resource *sc_csr;
struct resource *sc_mem;
struct rman sc_io_rman;
struct rman sc_mem_rman;
struct rman sc_irq_rman;
struct bus_space sc_pci_memt;
struct bus_space sc_pci_iot;
bus_dma_tag_t sc_dmat;
};
#define EXP_BUS_WRITE_4(sc, reg, data) \
bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data)
#define EXP_BUS_READ_4(sc, reg) \
bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg)
#define GPIO_CONF_WRITE_4(sc, reg, data) \
bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, reg, data)
#define GPIO_CONF_READ_4(sc, reg) \
bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
#define IXP4XX_GPIO_LOCK() mtx_lock(&ixp425_gpio_mtx)
#define IXP4XX_GPIO_UNLOCK() mtx_unlock(&ixp425_gpio_mtx)
extern struct mtx ixp425_gpio_mtx;
extern struct bus_space ixp425_bs_tag;
extern struct bus_space ixp425_a4x_bs_tag;
extern struct bus_space cambria_exp_bs_tag;
void cambria_exp_bus_init(struct ixp425_softc *);
void ixp425_io_bs_init(bus_space_tag_t, void *);
void ixp425_mem_bs_init(bus_space_tag_t, void *);
uint32_t ixp425_sdram_size(void);
uint32_t ixp435_ddram_size(void);
uint32_t ixp4xx_read_feature_bits(void);
void ixp4xx_write_feature_bits(uint32_t);
int ixp425_md_route_interrupt(device_t, device_t, int);
void ixp425_md_attach(device_t);
int getvbase(uint32_t, uint32_t, uint32_t *);
struct ixp425_ivar {
uint32_t addr;
int irq;
};
#define IXP425_IVAR(d) ((struct ixp425_ivar *) device_get_ivars(d))
enum {
IXP425_IVAR_ADDR, /* base physical address */
IXP425_IVAR_IRQ /* irq/gpio pin assignment */
};
#endif /* _IXP425VAR_H_ */

20
sys/arm/xscale/ixp425/std.avila
View File

@ -1,20 +0,0 @@
#$FreeBSD$
#
# Gateworks GW23XX board configuration
#
files "../xscale/ixp425/files.avila"
#
# Physical memory starts at 0. We assume images are loaded at
# 0x200000, e.g. from redboot with load -b 0x200000 kernel.
#
# Redboot is expected to handle unmapping the flash memory that
# appears at 0 on boot. Likewise we expect the expansion bus to
# be remapped away from 0.
#
options PHYSADDR=0x00000000
makeoptions KERNPHYSADDR=0x00200000
options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
makeoptions KERNVIRTADDR=0xc0200000
options FLASHADDR=0x50000000
options LOADERRAMADDR=0x00000000

5
sys/arm/xscale/ixp425/std.ixp425
View File

@ -1,5 +0,0 @@
#XScale IXP425 generic configuration
#$FreeBSD$
files "../xscale/ixp425/files.ixp425"
include "../xscale/std.xscale-be"
cpu CPU_XSCALE_IXP425

7
sys/arm/xscale/ixp425/std.ixp435
View File

@ -1,7 +0,0 @@
#XScale IXP435 generic configuration
#$FreeBSD$
files "../xscale/ixp425/files.ixp425"
include "../xscale/std.xscale-be"
cpu CPU_XSCALE_IXP435
cpu CPU_XSCALE_IXP425

84
sys/arm/xscale/ixp425/uart_bus_ixp425.c
View File

@ -1,84 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Kevin Lo. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/pci/pcivar.h>
#include <dev/ic/ns16550.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#include "uart_if.h"
static int uart_ixp425_probe(device_t dev);
static device_method_t uart_ixp425_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_ixp425_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{ 0, 0 }
};
static driver_t uart_ixp425_driver = {
uart_driver_name,
uart_ixp425_methods,
sizeof(struct uart_softc),
};
DRIVER_MODULE(uart, ixp, uart_ixp425_driver, uart_devclass, 0, 0);
static int
uart_ixp425_probe(device_t dev)
{
struct uart_softc *sc;
int unit = device_get_unit(dev);
u_int rclk;
sc = device_get_softc(dev);
sc->sc_class = &uart_ns8250_class;
if (resource_int_value("uart", unit, "rclk", &rclk))
rclk = IXP425_UART_FREQ;
if (bootverbose)
device_printf(dev, "rclk %u\n", rclk);
return uart_bus_probe(dev, 0, 0, rclk, 0, 0);
}

98
sys/arm/xscale/ixp425/uart_cpu_ixp425.c
View File

@ -1,98 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2003 Marcel Moolenaar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
uint32_t i, ivar, vaddr;
/*
* Scan the hints. The IXP425 only have 2 serial ports, so only
* scan them.
*/
for (i = 0; i < 2; i++) {
if (resource_int_value("uart", i, "flags", &ivar))
continue;
if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar))
continue;
if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar))
continue;
/*
* We have a possible device. Make sure it's enabled and
* that we have an I/O port.
*/
if (resource_int_value("uart", i, "disabled", &ivar) == 0 &&
ivar != 0)
continue;
if (resource_int_value("uart", i, "addr", &ivar) != 0 ||
ivar == 0)
continue;
/* Got it. Fill in the instance and return it. */
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = &ixp425_a4x_bs_tag;
di->bas.regshft = 0;
di->bas.rclk = IXP425_UART_FREQ;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = NULL;
uart_bus_space_mem = &ixp425_a4x_bs_tag;
getvbase(ivar, IXP425_REG_SIZE, &vaddr);
di->bas.bsh = vaddr;
return (0);
}
return (ENXIO);
}

5
sys/arm/xscale/std.xscale-be
View File

@ -1,5 +0,0 @@
#Big-Endian XScale generic configuration
#$FreeBSD$
include "../xscale/std.xscale"
machine arm armeb

4
sys/conf/files.arm
View File

@ -33,14 +33,14 @@ arm/arm/cpufunc_asm.S standard
arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e
arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176
arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176
arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342
arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_81342
arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e
arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176
arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b
arm/arm/cpufunc_asm_fa526.S optional cpu_fa526
arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b
arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e
arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342
arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_81342
arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342
arm/arm/cpuinfo.c standard
arm/arm/cpu_asm-v6.S optional armv7 | armv6

1
sys/conf/kern.mk
View File

@ -279,7 +279,6 @@ CFLAGS+= -std=${CSTD}
LD_EMULATION_aarch64=aarch64elf
LD_EMULATION_amd64=elf_x86_64_fbsd
LD_EMULATION_arm=armelf_fbsd
LD_EMULATION_armeb=armelfb_fbsd
LD_EMULATION_armv6=armelf_fbsd
LD_EMULATION_armv7=armelf_fbsd
LD_EMULATION_i386=elf_i386_fbsd

3
sys/conf/options.arm
View File

@ -17,8 +17,6 @@ CPU_KRAIT opt_global.h
CPU_FA526 opt_global.h
CPU_MV_PJ4B opt_global.h
CPU_XSCALE_81342 opt_global.h
CPU_XSCALE_IXP425 opt_global.h
CPU_XSCALE_IXP435 opt_global.h
CPU_XSCALE_PXA2X0 opt_global.h
SMP_ON_UP opt_global.h # Runtime detection of MP extensions
DEV_GIC opt_global.h
@ -30,7 +28,6 @@ INTRNG opt_global.h
IPI_IRQ_START opt_smp.h
IPI_IRQ_END opt_smp.h
FREEBSD_BOOT_LOADER opt_global.h
IXP4XX_FLASH_SIZE opt_global.h
KERNBASE opt_global.h
KERNVIRTADDR opt_global.h
LINUX_BOOT_ABI opt_global.h

82
sys/dev/cfi/cfi_bus_ixp4xx.c
View File

@ -1,82 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009 Roelof Jonkman, Carlson Wireless Inc.
* Copyright (c) 2009 Sam Leffler, Errno Consulting
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <dev/cfi/cfi_var.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
static int
cfi_ixp4xx_probe(device_t dev)
{
struct cfi_softc *sc = device_get_softc(dev);
/*
* NB: we assume the boot loader sets up EXP_TIMING_CS0_OFFSET
* according to the flash on the board. If it does not then it
* can be done here.
*/
if (bootverbose) {
struct ixp425_softc *sa =
device_get_softc(device_get_parent(dev));
device_printf(dev, "EXP_TIMING_CS0_OFFSET 0x%x\n",
EXP_BUS_READ_4(sa, EXP_TIMING_CS0_OFFSET));
}
sc->sc_width = 2; /* NB: don't probe interface width */
return cfi_probe(dev);
}
static device_method_t cfi_ixp4xx_methods[] = {
/* device interface */
DEVMETHOD(device_probe, cfi_ixp4xx_probe),
DEVMETHOD(device_attach, cfi_attach),
DEVMETHOD(device_detach, cfi_detach),
DEVMETHOD_END
};
static driver_t cfi_ixp4xx_driver = {
cfi_driver_name,
cfi_ixp4xx_methods,
sizeof(struct cfi_softc),
};
DRIVER_MODULE(cfi, ixp, cfi_ixp4xx_driver, cfi_devclass, 0, 0);

3
sys/dev/hwpmc/hwpmc_xscale.h
View File

@ -42,9 +42,6 @@
#define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */
#define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */
#define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */
/* IXP425 only -- first generation */
#define XSCALE_PMNC_EVT0_MASK 0x00ff000
#define XSCALE_PMNC_EVT1_MASK 0xff00000
#define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */
#define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */

323
sys/dev/usb/controller/ehci_ixp4xx.c
View File

@ -1,323 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2008 Sam Leffler. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* IXP435 attachment driver for the USB Enhanced Host Controller.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_bus.h"
#include <sys/stdint.h>
#include <sys/stddef.h>
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/sysctl.h>
#include <sys/sx.h>
#include <sys/unistd.h>
#include <sys/callout.h>
#include <sys/malloc.h>
#include <sys/priv.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usb_core.h>
#include <dev/usb/usb_busdma.h>
#include <dev/usb/usb_process.h>
#include <dev/usb/usb_util.h>
#include <dev/usb/usb_controller.h>
#include <dev/usb/usb_bus.h>
#include <dev/usb/controller/ehci.h>
#include <dev/usb/controller/ehcireg.h>
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
#define EHCI_VENDORID_IXP4XX 0x42fa05
#define EHCI_HC_DEVSTR "IXP4XX Integrated USB 2.0 controller"
struct ixp_ehci_softc {
ehci_softc_t base; /* storage for EHCI code */
bus_space_tag_t iot;
bus_space_handle_t ioh;
struct bus_space tag; /* tag for private bus space ops */
};
static device_attach_t ehci_ixp_attach;
static device_detach_t ehci_ixp_detach;
static uint8_t ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t);
static uint16_t ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint16_t);
static uint32_t ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t);
static void ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint32_t);
static void
ehci_ixp_post_reset(struct ehci_softc *ehci_softc)
{
uint32_t usbmode;
/* Force HOST mode, select big-endian mode */
usbmode = EOREAD4(ehci_softc, EHCI_USBMODE_NOLPM);
usbmode &= ~EHCI_UM_CM;
usbmode |= EHCI_UM_CM_HOST;
usbmode |= EHCI_UM_ES_BE;
EOWRITE4(ehci_softc, EHCI_USBMODE_NOLPM, usbmode);
}
static int
ehci_ixp_probe(device_t self)
{
device_set_desc(self, EHCI_HC_DEVSTR);
return (BUS_PROBE_DEFAULT);
}
static int
ehci_ixp_attach(device_t self)
{
struct ixp_ehci_softc *isc = device_get_softc(self);
ehci_softc_t *sc = &isc->base;
int err;
int rid;
/* initialise some bus fields */
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
return (ENOMEM);
}
/* NB: hints fix the memory location and irq */
rid = 0;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
/*
* Craft special resource for bus space ops that handle
* byte-alignment of non-word addresses. Also, since
* we're already intercepting bus space ops we handle
* the register window offset that could otherwise be
* done with bus_space_subregion.
*/
isc->iot = rman_get_bustag(sc->sc_io_res);
isc->tag.bs_privdata = isc->iot;
/* read single */
isc->tag.bs_r_1 = ehci_bs_r_1;
isc->tag.bs_r_2 = ehci_bs_r_2;
isc->tag.bs_r_4 = ehci_bs_r_4;
/* write (single) */
isc->tag.bs_w_1 = ehci_bs_w_1;
isc->tag.bs_w_2 = ehci_bs_w_2;
isc->tag.bs_w_4 = ehci_bs_w_4;
sc->sc_io_tag = &isc->tag;
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
sc->sc_io_size = IXP435_USB1_SIZE - 0x100;
rid = 0;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR);
sprintf(sc->sc_vendor, "Intel");
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
/*
* Select big-endian byte alignment and arrange to not terminate
* reset operations (the adapter will ignore it if we do but might
* as well save a reg write). Also, the controller has an embedded
* Transaction Translator which means port speed must be read from
* the Port Status register following a port enable.
*/
sc->sc_flags |= EHCI_SCFLG_TT
| EHCI_SCFLG_BIGEDESC
| EHCI_SCFLG_NORESTERM
;
/* Setup callbacks. */
sc->sc_vendor_post_reset = ehci_ixp_post_reset;
sc->sc_vendor_get_port_speed = ehci_get_port_speed_portsc;
err = ehci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
goto error;
}
return (0);
error:
ehci_ixp_detach(self);
return (ENXIO);
}
static int
ehci_ixp_detach(device_t self)
{
struct ixp_ehci_softc *isc = device_get_softc(self);
ehci_softc_t *sc = &isc->base;
int err;
/* during module unload there are lots of children leftover */
device_delete_children(self);
if (sc->sc_irq_res && sc->sc_intr_hdl) {
/*
* only call ehci_detach() after ehci_init()
*/
ehci_detach(sc);
err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
if (err)
/* XXX or should we panic? */
device_printf(self, "Could not tear down irq, %d\n",
err);
sc->sc_intr_hdl = NULL;
}
if (sc->sc_irq_res) {
bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
sc->sc_irq_res = NULL;
}
if (sc->sc_io_res) {
bus_release_resource(self, SYS_RES_MEMORY, 0,
sc->sc_io_res);
sc->sc_io_res = NULL;
}
usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
return (0);
}
/*
* Bus space accessors for PIO operations.
*/
static uint8_t
ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
return bus_space_read_1((bus_space_tag_t)tag->bs_privdata, h,
0x100 + (o &~ 3) + (3 - (o & 3)));
}
static void
ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v)
{
panic("%s", __func__);
}
static uint16_t
ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
return bus_space_read_2((bus_space_tag_t)tag->bs_privdata, h,
0x100 + (o &~ 3) + (2 - (o & 3)));
}
static void
ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v)
{
panic("%s", __func__);
}
static uint32_t
ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o)
{
return bus_space_read_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o);
}
static void
ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint32_t v)
{
bus_space_write_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o, v);
}
static device_method_t ehci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ehci_ixp_probe),
DEVMETHOD(device_attach, ehci_ixp_attach),
DEVMETHOD(device_detach, ehci_ixp_detach),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD_END
};
static driver_t ehci_driver = {
"ehci",
ehci_methods,
sizeof(struct ixp_ehci_softc),
};
static devclass_t ehci_devclass;
DRIVER_MODULE(ehci, ixp, ehci_driver, ehci_devclass, 0, 0);
MODULE_DEPEND(ehci, usb, 1, 1, 1);

9
sys/modules/cfi/Makefile
View File

@ -3,16 +3,9 @@
.PATH: ${SRCTOP}/sys/dev/cfi
KMOD= cfi
SRCS= ${_cfi_bus} cfi_core.c cfi_dev.c
SRCS= cfi_bus_fdt.c ofw_bus_if.h cfi_core.c cfi_dev.c
SRCS+= bus_if.h device_if.h opt_cfi.h
.if ${MACHINE} == "arm"
_cfi_bus= cfi_bus_fdt.c cfi_bus_ixp4xx.c ofw_bus_if.h
.endif
.if ${MACHINE} == "powerpc"
_cfi_bus= cfi_bus_fdt.c ofw_bus_if.h
.endif
opt_cfi.h:
echo "#define CFI_SUPPORT_STRATAFLASH 1" > ${.TARGET}