Connect twi to the FreeBSD iicbus infrastructure.
This commit is contained in:
imp
parent
b8ec0fd91c
commit
000b33975f
@ -40,7 +40,10 @@ __FBSDID("$FreeBSD$");
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_twireg.h>
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#include <arm/at91/at91_twiio.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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struct at91_twi_softc
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{
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@ -50,13 +53,12 @@ struct at91_twi_softc
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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int flags;
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#define XFER_PENDING 1 /* true when transfer taking place */
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#define OPENED 2 /* Device opened */
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#define RXRDY 4
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#define TXCOMP 8
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#define TXRDY 0x10
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struct cdev *cdev;
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uint32_t cwgr;
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int sc_started;
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int twi_addr;
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device_t iicbus;
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};
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static inline uint32_t
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@ -79,7 +81,6 @@ WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val)
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#define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define CDEV2SOFTC(dev) ((dev)->si_drv1)
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#define TWI_DEF_CLK 100000
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static devclass_t at91_twi_devclass;
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@ -95,19 +96,6 @@ static void at91_twi_intr(void *);
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static int at91_twi_activate(device_t dev);
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static void at91_twi_deactivate(device_t dev);
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/* cdev routines */
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static d_open_t at91_twi_open;
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static d_close_t at91_twi_close;
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static d_ioctl_t at91_twi_ioctl;
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static struct cdevsw at91_twi_cdevsw =
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{
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.d_version = D_VERSION,
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.d_open = at91_twi_open,
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.d_close = at91_twi_close,
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.d_ioctl = at91_twi_ioctl
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};
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static int
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at91_twi_probe(device_t dev)
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{
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@ -137,20 +125,23 @@ at91_twi_attach(device_t dev)
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AT91_TWI_LOCK_DESTROY(sc);
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goto out;
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}
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sc->cdev = make_dev(&at91_twi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
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"twi%d", device_get_unit(dev));
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if (sc->cdev == NULL) {
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err = ENOMEM;
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goto out;
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}
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sc->cdev->si_drv1 = sc;
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sc->cwgr = TWI_CWGR_CKDIV(1) |
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sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / 90000) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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WR4(sc, TWI_IER, TWI_SR_RXRDY | TWI_SR_OVRE | TWI_SR_UNRE |
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TWI_SR_NACK);
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if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
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device_printf(dev, "could not allocate iicbus instance\n");
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/* probe and attach the iicbus */
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bus_generic_attach(dev);
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out:;
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if (err)
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at91_twi_deactivate(dev);
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@ -160,7 +151,15 @@ out:;
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static int
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at91_twi_detach(device_t dev)
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{
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return (EBUSY); /* XXX */
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struct at91_twi_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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at91_twi_deactivate(dev);
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if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0)
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return (rv);
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return (0);
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}
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static int
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@ -215,13 +214,12 @@ at91_twi_intr(void *xsc)
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/* Reading the status also clears the interrupt */
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status = RD4(sc, TWI_SR);
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printf("status %x\n", status);
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if (status == 0)
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return;
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AT91_TWI_LOCK(sc);
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if (status & TWI_SR_RXRDY)
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sc->flags |= RXRDY;
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if (status & TWI_SR_TXCOMP)
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sc->flags |= TXCOMP;
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if (status & TWI_SR_TXRDY)
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sc->flags |= TXRDY;
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AT91_TWI_UNLOCK(sc);
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@ -229,191 +227,196 @@ at91_twi_intr(void *xsc)
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return;
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}
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static int
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at91_twi_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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struct at91_twi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_TWI_LOCK(sc);
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if (!(sc->flags & OPENED)) {
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sc->flags |= OPENED;
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WR4(sc, TWI_IER, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
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TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
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}
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AT91_TWI_UNLOCK(sc);
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return (0);
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}
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static int
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at91_twi_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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at91_twi_wait_stop_done(struct at91_twi_softc *sc)
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{
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struct at91_twi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_TWI_LOCK(sc);
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sc->flags &= ~OPENED;
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WR4(sc, TWI_IDR, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
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TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
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AT91_TWI_UNLOCK(sc);
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return (0);
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}
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static int
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at91_twi_read_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
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{
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err = 0;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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RD4(sc, TWI_RHR);
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// Master mode, with the right address and interal addr size
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WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MREAD |
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TWI_MMR_DADR(xfr->dadr));
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WR4(sc, TWI_IADR, xfr->iadr);
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WR4(sc, TWI_CR, TWI_CR_START);
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while (len-- > 1) {
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while (!(sc->flags & RXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
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0);
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if (err)
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return (err);
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}
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sc->flags &= ~RXRDY;
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*walker++ = RD4(sc, TWI_RHR) & 0xff;
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}
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WR4(sc, TWI_CR, TWI_CR_STOP);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird2", 0);
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if (err)
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return (err);
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}
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sc->flags &= ~TXCOMP;
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*walker = RD4(sc, TWI_RHR) & 0xff;
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if (xfr->xfer_buf) {
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AT91_TWI_UNLOCK(sc);
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err = copyout(buffer, xfr->xfer_buf, xfr->xfer_len);
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AT91_TWI_LOCK(sc);
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while (!(RD4(sc, TWI_SR) & TWI_SR_TXCOMP))
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continue;
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return (err);
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}
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/*
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* Stop the transfer by entering a STOP state on the iic bus. For read
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* operations, we've already entered the STOP state, since we need to do
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* that to read the last character. For write operations, we need to
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* wait for the TXCOMP bit to turn on before returning.
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*/
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static int
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at91_twi_stop(device_t dev)
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{
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struct at91_twi_softc *sc;
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int err = 0;
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sc = device_get_softc(dev);
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if (sc->sc_started) {
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WR4(sc, TWI_CR, TWI_CR_STOP);
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err = at91_twi_wait_stop_done(sc);
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}
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return (err);
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}
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/*
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* enter a START condition without requiring the device to be in a STOP
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* state.
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*/
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static int
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at91_twi_write_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
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at91_twi_repeated_start(device_t dev, u_char slave, int timeout)
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{
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err;
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struct at91_twi_softc *sc;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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AT91_TWI_UNLOCK(sc);
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err = copyin(xfr->xfer_buf, buffer, xfr->xfer_len);
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sc = device_get_softc(dev);
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WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
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WR4(sc, TWI_CR, TWI_CR_START);
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sc->sc_started = 1;
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return (0);
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}
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/*
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* enter a START condition from an idle state.
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*/
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static int
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at91_twi_start(device_t dev, u_char slave, int timeout)
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{
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struct at91_twi_softc *sc;
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sc = device_get_softc(dev);
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WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
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WR4(sc, TWI_CR, TWI_CR_START);
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sc->sc_started = 1;
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return (0);
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}
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static int
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at91_twi_write(device_t dev, char *buf, int len, int *sent, int timeout /* us */)
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{
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struct at91_twi_softc *sc;
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uint8_t *walker;
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int err = 0;
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walker = buf;
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sc = device_get_softc(dev);
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WR4(sc, TWI_MMR, TWI_MMR_MWRITE | RD4(sc, TWI_MMR));
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AT91_TWI_LOCK(sc);
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if (err)
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return (err);
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/* Setup the xfr for later readback */
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xfr->xfer_buf = 0;
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xfr->xfer_len = 1;
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WR4(sc, TWI_IER, TWI_SR_TXRDY);
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while (len--) {
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WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MWRITE |
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TWI_MMR_DADR(xfr->dadr));
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WR4(sc, TWI_IADR, xfr->iadr++);
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WR4(sc, TWI_THR, *walker++);
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WR4(sc, TWI_CR, TWI_CR_START);
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/*
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* If we get signal while waiting for TXRDY, make sure we
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* try to stop this device
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*/
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while (!(sc->flags & TXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr",
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0);
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if (err)
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break;
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goto errout;
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}
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if (err)
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return (err);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr2",
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0);
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if (err)
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return (err);
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}
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/* Readback */
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at91_twi_read_master(sc, xfr);
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}
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errout:;
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WR4(sc, TWI_IDR, TWI_SR_TXRDY);
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AT91_TWI_UNLOCK(sc);
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return (err);
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}
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static int
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at91_twi_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td)
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at91_twi_read(device_t dev, char *buf, int len, int *read, int last,
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int delay /* us */)
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{
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int err = 0;
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struct at91_twi_softc *sc;
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char *walker;
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int err = 0;
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sc = CDEV2SOFTC(dev);
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walker = buf;
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sc = device_get_softc(dev);
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AT91_TWI_LOCK(sc);
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while (sc->flags & XFER_PENDING) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH,
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"twiwait", 0);
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if (err) {
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AT91_TWI_UNLOCK(sc);
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return (err);
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WR4(sc, TWI_MMR, ~TWI_MMR_MWRITE & RD4(sc, TWI_MMR));
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WR4(sc, TWI_IER, TWI_SR_RXRDY);
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while (len-- > 0) {
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err = 0;
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while (!(sc->flags & RXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
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0);
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if (err)
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goto errout;
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}
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}
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sc->flags |= XFER_PENDING;
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switch (cmd)
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{
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case TWIIOCXFER:
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{
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struct at91_twi_io *xfr = (struct at91_twi_io *)data;
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switch (xfr->type)
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{
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case TWI_IO_READ_MASTER:
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err = at91_twi_read_master(sc, xfr);
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sc->flags &= ~RXRDY;
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*walker++ = RD4(sc, TWI_RHR) & 0xff;
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if (len == 1 && last)
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break;
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case TWI_IO_WRITE_MASTER:
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err = at91_twi_write_master(sc, xfr);
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break;
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default:
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err = EINVAL;
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break;
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}
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break;
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}
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case TWIIOCSETCLOCK:
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{
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struct at91_twi_clock *twick = (struct at91_twi_clock *)data;
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sc->cwgr = TWI_CWGR_CKDIV(twick->ckdiv) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(twick->high_rate)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(twick->low_rate));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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break;
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}
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default:
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err = ENOTTY;
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break;
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}
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sc->flags &= ~XFER_PENDING;
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if (!last)
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goto errout;
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WR4(sc, TWI_CR, TWI_CR_STOP);
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err = at91_twi_wait_stop_done(sc);
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*walker = RD4(sc, TWI_RHR) & 0xff;
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if (read)
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*read = walker - buf;
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sc->sc_started = 0;
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errout:;
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WR4(sc, TWI_IDR, TWI_SR_RXRDY);
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AT91_TWI_UNLOCK(sc);
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wakeup(sc);
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return err;
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return (err);
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}
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static int
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at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct at91_twi_softc *sc;
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int ckdiv, rate;
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sc = device_get_softc(dev);
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if (oldaddr)
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*oldaddr = sc->twi_addr;
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if (addr != 0)
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sc->twi_addr = 0;
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else
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sc->twi_addr = addr;
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rate = 1;
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/*
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* 8 * is because "rate == 1" -> 4 clocks down, 4 clocks up. The
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* speeds are for 1.5kb/s, 45kb/s and 90kb/s.
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*/
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switch (speed) {
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case IIC_SLOW:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 1500;
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break;
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case IIC_FAST:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 45000;
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break;
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case IIC_UNKNOWN:
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case IIC_FASTEST:
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default:
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ckdiv = 8 * AT91C_MASTER_CLOCK / 90000;
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break;
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}
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sc->cwgr = TWI_CWGR_CKDIV(ckdiv) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(rate)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(rate));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
|
||||
WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
|
||||
WR4(sc, TWI_CWGR, sc->cwgr);
|
||||
|
||||
return EIO;
|
||||
}
|
||||
|
||||
static int
|
||||
at91_twi_callback(device_t dev, int index, caddr_t *data)
|
||||
{
|
||||
int error = 0;
|
||||
|
||||
switch (index) {
|
||||
case IIC_REQUEST_BUS:
|
||||
break;
|
||||
|
||||
case IIC_RELEASE_BUS:
|
||||
break;
|
||||
|
||||
default:
|
||||
error = EINVAL;
|
||||
}
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
static device_method_t at91_twi_methods[] = {
|
||||
@ -422,6 +425,14 @@ static device_method_t at91_twi_methods[] = {
|
||||
DEVMETHOD(device_attach, at91_twi_attach),
|
||||
DEVMETHOD(device_detach, at91_twi_detach),
|
||||
|
||||
/* iicbus interface */
|
||||
DEVMETHOD(iicbus_callback, at91_twi_callback),
|
||||
DEVMETHOD(iicbus_repeated_start, at91_twi_repeated_start),
|
||||
DEVMETHOD(iicbus_start, at91_twi_start),
|
||||
DEVMETHOD(iicbus_stop, at91_twi_stop),
|
||||
DEVMETHOD(iicbus_write, at91_twi_write),
|
||||
DEVMETHOD(iicbus_read, at91_twi_read),
|
||||
DEVMETHOD(iicbus_reset, at91_twi_rst_card),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user