From 003df2a90f89d71a96e506635e86f27b0075c5e0 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Thu, 12 May 2011 03:25:24 +0000 Subject: [PATCH] Fix the half/quater rate PLL setup for AR5416, AR9160 and (beta?) AR9280 chips. Note: This doesn't "fix" half/quarter rate support for these chips; it merely fixes an oversight. Obtained from: Atheros --- sys/dev/ath/ath_hal/ar5416/ar5416_reset.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c index 55629243be26..c57e6b985ca0 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c @@ -1389,10 +1389,12 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); else if (IEEE80211_IS_CHAN_QUARTER(chan)) pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); - else if (IEEE80211_IS_CHAN_5GHZ(chan)) + + if (IEEE80211_IS_CHAN_5GHZ(chan)) pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); else pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); + } else pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); } else if (AR_SREV_SOWL_10_OR_LATER(ah)) { @@ -1402,7 +1404,8 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); else if (IEEE80211_IS_CHAN_QUARTER(chan)) pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); - else if (IEEE80211_IS_CHAN_5GHZ(chan)) + + if (IEEE80211_IS_CHAN_5GHZ(chan)) pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); else pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); @@ -1415,7 +1418,8 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) pll |= SM(0x1, AR_RTC_PLL_CLKSEL); else if (IEEE80211_IS_CHAN_QUARTER(chan)) pll |= SM(0x2, AR_RTC_PLL_CLKSEL); - else if (IEEE80211_IS_CHAN_5GHZ(chan)) + + if (IEEE80211_IS_CHAN_5GHZ(chan)) pll |= SM(0xa, AR_RTC_PLL_DIV); else pll |= SM(0xb, AR_RTC_PLL_DIV);