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Create macros for the MAIR memory attributes. While here add an uncached

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memory type, however the VM code still needs to be taught about this.

MFC after:	1 week
Sponsored by:	ABT Systems Ltd
This commit is contained in:
andrew 2016-10-14 22:20:14 +00:00
parent 22e05c4848
commit 0058087fc0
2 changed files with 8 additions and 2 deletions
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6
sys/arm64/arm64/locore.S
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@ -617,8 +617,10 @@ start_mmu:
.align 3
mair:
/* Device Normal, no cache Normal, write-back */
.quad MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2)
.quad MAIR_ATTR(MAIR_DEVICE_nGnRnE, 0) | \
MAIR_ATTR(MAIR_NORMAL_NC, 1) | \
MAIR_ATTR(MAIR_NORMAL_WB, 2) | \
MAIR_ATTR(MAIR_NORMAL_WT, 3)
tcr:
.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
TCR_CACHE_ATTRS | TCR_SMP_ATTRS)

4
sys/arm64/include/armreg.h
View File

@ -357,6 +357,10 @@
/* MAIR_EL1 - Memory Attribute Indirection Register */
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0x88
#define MAIR_NORMAL_WB 0xff
/* PAR_EL1 - Physical Address Register */
#define PAR_F_SHIFT 0