- According to Linux, the ALi M5451 can do 31-bit DMA instead of just
30-bit like the reset of the controllers supported by this driver. Actually ALi M5451 can be setup up to generate 32-bit addresses by setting the 31st bit via the accompanying ISA bridge, which allows it to work in sparc64 machines whose IOMMU require at least 32-bit DMA. Even though other architectures would also benefit from 32-bit DMA, enabling this bit is limited to sparc64 as bus_dma(9) doesn't generally guarantee that a low address of BUS_SPACE_MAXADDR_32BIT results in a buffer in the 32-bit range. - According to Tatsuo YOKOGAWA's ali(4), the the DMA transfer size of ALi M5451 is fixed to 64k and in fact using the default size of 4k - The 4DWAVE DX and NX require the recording buffer to be 8-byte aligned so adjust the bus_dma_tag_create(9) accordingly. - Unlike the rest of the controllers supported by this driver, the ALi M5451 only has 32 hardware channels instead of 64 so limit the loop in tr_intr() accordingly. [1] Submitted by: yongari [1] Reviewed by: yongari (superset of what is committed) MFC after: 3 days
This commit is contained in:
marius
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f6bdb09ba4
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0110876eec
@ -45,18 +45,22 @@ SND_DECLARE_FILE("$FreeBSD$");
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#define SPA_PCI_ID 0x70181039
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#define TR_DEFAULT_BUFSZ 0x1000
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/* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */
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#define ALI_BUFSZ 0x10000
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#define TR_BUFALGN 0x8
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#define TR_TIMEOUT_CDC 0xffff
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#define TR_MAXHWCH 64
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#define ALI_MAXHWCH 32
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#define TR_MAXPLAYCH 4
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#define ALI_MAXPLAYCH 1
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/*
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* Though, it's not clearly documented in trident datasheet, trident
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* audio cards can't handle DMA addresses located above 1GB. The LBA
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* (loop begin address) register which holds DMA base address is 32bits
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* register.
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* But the MSB 2bits are used for other purposes(I guess it is really
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* bad idea). This effectivly limits the DMA address space up to 1GB.
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* Though, it's not clearly documented in the 4DWAVE datasheet, the
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* DX and NX chips can't handle DMA addresses located above 1GB as the
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* LBA (loop begin address) register which holds the DMA base address
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* is 32-bit, but the two MSBs are used for other purposes.
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*/
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#define TR_MAXADDR ((1 << 30) - 1)
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#define TR_MAXADDR ((1U << 30) - 1)
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#define ALI_MAXADDR ((1U << 31) - 1)
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struct tr_info;
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@ -97,6 +101,7 @@ struct tr_info {
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struct mtx *lock;
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u_int32_t hwchns;
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u_int32_t playchns;
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unsigned int bufsz;
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@ -398,7 +403,10 @@ tr_wrch(struct tr_chinfo *ch)
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ch->ec &= 0x00000fff;
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ch->alpha &= 0x00000fff;
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ch->delta &= 0x0000ffff;
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ch->lba &= 0x3fffffff;
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if (tr->type == ALI_PCI_ID)
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ch->lba &= ALI_MAXADDR;
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else
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ch->lba &= TR_MAXADDR;
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cr[1]=ch->lba;
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cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
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@ -441,7 +449,10 @@ tr_rdch(struct tr_chinfo *ch)
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snd_mtxunlock(tr->lock);
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ch->lba= (cr[1] & 0x3fffffff);
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if (tr->type == ALI_PCI_ID)
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ch->lba=(cr[1] & ALI_MAXADDR);
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else
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ch->lba=(cr[1] & TR_MAXADDR);
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ch->fmc= (cr[3] & 0x0000c000) >> 14;
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ch->rvol= (cr[3] & 0x00003f80) >> 7;
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ch->cvol= (cr[3] & 0x0000007f);
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@ -628,7 +639,6 @@ trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
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tr_wr(tr, TR_REG_SBCTRL, i, 1);
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return 0;
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}
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static u_int32_t
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@ -729,7 +739,7 @@ tr_intr(void *p)
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intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
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if (intsrc & TR_INT_ADDR) {
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chnum = 0;
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while (chnum < 64) {
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while (chnum < tr->hwchns) {
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mask = 0x00000001;
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active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
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bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
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@ -815,8 +825,13 @@ tr_pci_attach(device_t dev)
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u_int32_t data;
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struct tr_info *tr;
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struct ac97_info *codec = 0;
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bus_addr_t lowaddr;
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int i, dacn;
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char status[SND_STATUSLEN];
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#ifdef __sparc64__
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device_t *children;
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int nchildren;
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#endif
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tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
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tr->type = pci_get_devid(dev);
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@ -834,7 +849,7 @@ tr_pci_attach(device_t dev)
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} else {
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switch (tr->type) {
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case ALI_PCI_ID:
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dacn = 1;
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dacn = ALI_MAXPLAYCH;
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break;
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default:
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dacn = TR_MAXPLAYCH;
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@ -859,8 +874,6 @@ tr_pci_attach(device_t dev)
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goto bad;
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}
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tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ, 65536);
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if (tr_init(tr) == -1) {
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device_printf(dev, "unable to initialize the card\n");
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goto bad;
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@ -879,12 +892,59 @@ tr_pci_attach(device_t dev)
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goto bad;
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}
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if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
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if (tr->type == ALI_PCI_ID) {
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/*
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* The M5451 generates 31 bit of DMA and in order to do
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* 32-bit DMA, the 31st bit can be set via its accompanying
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* ISA bridge. Note that we can't predict whether bus_dma(9)
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* will actually supply us with a 32-bit buffer and even when
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* using a low address of BUS_SPACE_MAXADDR_32BIT for both
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* we might end up with the play buffer being in the 32-bit
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* range while the record buffer isn't or vice versa. So we
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* limit enabling the 31st bit to sparc64, where the IOMMU
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* guarantees that we're using a 32-bit address (and in turn
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* requires it).
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*/
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lowaddr = ALI_MAXADDR;
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#ifdef __sparc64__
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if (device_get_children(device_get_parent(dev), &children,
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&nchildren) == 0) {
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == 0x153310b9) {
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lowaddr = BUS_SPACE_MAXADDR_32BIT;
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data = pci_read_config(children[i],
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0x7e, 1);
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if (bootverbose)
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device_printf(dev,
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"M1533 0x7e: 0x%x -> ",
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data);
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data |= 0x1;
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if (bootverbose)
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printf("0x%x\n", data);
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pci_write_config(children[i], 0x7e,
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data, 1);
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break;
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}
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}
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}
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free(children, M_TEMP);
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#endif
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tr->hwchns = ALI_MAXHWCH;
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tr->bufsz = ALI_BUFSZ;
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} else {
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lowaddr = TR_MAXADDR;
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tr->hwchns = TR_MAXHWCH;
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tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ,
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65536);
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}
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if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
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/*alignment*/TR_BUFALGN,
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/*boundary*/0,
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/*lowaddr*/TR_MAXADDR,
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/*lowaddr*/lowaddr,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
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/*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz,
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/*flags*/0, /*lockfunc*/busdma_lock_mutex,
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/*lockarg*/&Giant, &tr->parent_dmat) != 0) {
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device_printf(dev, "unable to create dma tag\n");
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