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Powerpc64: Add the facility unavailable trap subsystem

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Summary:
This code adds the basic infrastructure for the facility subsystem. A facility
trap is raised when an unavailable instruction is executed. One example is
executing a Hardware Transactional Memory instruction while the MSR[TM] is
disabled. In the past, there was a specific interrupt for it (FP, VEC), but the
new instructions seem to be multiplexed on this facility interrupt.

The root cause of the trap is provided on Facility Status and Control Register
(FSCR) register.

Submitted by:	Breno Leitao
Reviewed by:	nwhitehorn
Differential Revision: https://reviews.freebsd.org/D14566
This commit is contained in:
jhibbits 2018-04-08 19:11:25 +00:00
parent c68f7df1ad
commit 0158b02fda
2 changed files with 22 additions and 0 deletions
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14
sys/powerpc/include/spr.h
View File

@ -120,6 +120,20 @@
#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
#define SPR_FSCR 0x099 /* Facility Status and Control Register */
#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */
#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */
#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */
#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */
#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */
#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */
#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */
/* Reserved 0x0500000000000000ULL */
#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
#define SPR_SPRG0 0x110 /* 468 SPR General 0 */

8
sys/powerpc/powerpc/trap.c
View File

@ -204,6 +204,7 @@ trap(struct trapframe *frame)
int sig, type, user;
u_int ucode;
ksiginfo_t ksi;
register_t fscr;
VM_CNT_INC(v_trap);
@ -294,6 +295,13 @@ trap(struct trapframe *frame)
break;
case EXC_FAC:
fscr = mfspr(SPR_FSCR);
if ((fscr & FSCR_IC_MASK) == FSCR_IC_HTM) {
CTR0(KTR_TRAP, "Hardware Transactional Memory subsystem disabled");
}
sig = SIGILL;
ucode = ILL_ILLOPC;
break;
case EXC_HEA:
sig = SIGILL;
ucode = ILL_ILLOPC;