Make ofwfb not be painfully slow. This reduces the time for a verbose boot
on my G4 iBook by more than half. Still 10% slower than syscons, but that's much better than a factor of 2. The slowness had to do with pathological write performance on 8-bit framebuffers, which are almost universally used on Open Firmware systems. Writing 1 byte at a time, potentially nonconsecutively, resulted in many extra PCI write cycles. This patch, in the common case where it's writing one or several characters in an 8x8 font, gangs the writes together into a set of 32-bit writes. This is a port of r143830 to vt(4). The EFI framebuffer is also extremely slow, probably for the same reason, and the same patch will likely help there.
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@ -136,6 +136,10 @@ ofwfb_bitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask,
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uint32_t fgc, bgc;
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int c;
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uint8_t b, m;
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union {
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uint32_t l;
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uint8_t c[4];
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} ch1, ch2;
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fgc = sc->sc_colormap[fg];
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bgc = sc->sc_colormap[bg];
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@ -147,36 +151,70 @@ ofwfb_bitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask,
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return;
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line = (sc->sc_stride * top) + left * sc->sc_depth/8;
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for (; height > 0; height--) {
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for (c = 0; c < width; c++) {
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if (c % 8 == 0)
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if (mask == NULL && sc->sc_depth == 8 && (width % 8 == 0)) {
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for (; height > 0; height--) {
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for (c = 0; c < width; c += 8) {
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b = *src++;
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else
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b <<= 1;
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if (mask != NULL) {
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if (c % 8 == 0)
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m = *mask++;
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else
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m <<= 1;
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/* Skip pixel write, if mask has no bit set. */
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if ((m & 0x80) == 0)
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continue;
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}
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switch(sc->sc_depth) {
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case 8:
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*(uint8_t *)(sc->sc_addr + line + c) =
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b & 0x80 ? fg : bg;
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break;
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case 32:
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*(uint32_t *)(sc->sc_addr + line + 4*c) =
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(b & 0x80) ? fgc : bgc;
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break;
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default:
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/* panic? */
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break;
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/*
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* Assume that there is more background than
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* foreground in characters and init accordingly
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*/
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ch1.l = ch2.l = (bg << 24) | (bg << 16) |
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(bg << 8) | bg;
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/*
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* Calculate 2 x 4-chars at a time, and then
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* write these out.
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*/
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if (b & 0x80) ch1.c[0] = fg;
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if (b & 0x40) ch1.c[1] = fg;
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if (b & 0x20) ch1.c[2] = fg;
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if (b & 0x10) ch1.c[3] = fg;
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if (b & 0x08) ch2.c[0] = fg;
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if (b & 0x04) ch2.c[1] = fg;
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if (b & 0x02) ch2.c[2] = fg;
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if (b & 0x01) ch2.c[3] = fg;
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*(uint32_t *)(sc->sc_addr + line + c) = ch1.l;
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*(uint32_t *)(sc->sc_addr + line + c + 4) =
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ch2.l;
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}
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line += sc->sc_stride;
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}
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} else {
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for (; height > 0; height--) {
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for (c = 0; c < width; c++) {
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if (c % 8 == 0)
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b = *src++;
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else
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b <<= 1;
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if (mask != NULL) {
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if (c % 8 == 0)
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m = *mask++;
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else
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m <<= 1;
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/* Skip pixel write, if mask not set. */
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if ((m & 0x80) == 0)
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continue;
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}
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switch(sc->sc_depth) {
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case 8:
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*(uint8_t *)(sc->sc_addr + line + c) =
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b & 0x80 ? fg : bg;
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break;
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case 32:
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*(uint32_t *)(sc->sc_addr + line + 4*c)
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= (b & 0x80) ? fgc : bgc;
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break;
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default:
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/* panic? */
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break;
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}
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}
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line += sc->sc_stride;
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}
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line += sc->sc_stride;
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}
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}
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