Changes for pci and pci-e support
- add bus_space_rmi_pci.c for PCI bus space - files.xlr update for changes in files - pcibus.c merged into xlr_pci.c (they were small files with inter-dependencies) - xlr_pci.c - lot of changes here with few fixes, formatting cleanup Obtained from: C. Jayachandran (JC) - c.jayachandran@gmail.com
This commit is contained in:
Randall Stewart
parent
219c125a72
commit
019ee9781a
@ -1,3 +1,764 @@
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/*-
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* Copyright (c) 2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/ktr.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cache.h>
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static int
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rmi_pci_bus_space_map(void *t, bus_addr_t addr,
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bus_size_t size, int flags,
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bus_space_handle_t * bshp);
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static void
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rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh,
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bus_size_t size);
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static int
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rmi_pci_bus_space_subregion(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, bus_size_t size,
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bus_space_handle_t * nbshp);
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static u_int8_t
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rmi_pci_bus_space_read_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset);
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static u_int16_t
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rmi_pci_bus_space_read_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset);
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static u_int32_t
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rmi_pci_bus_space_read_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset);
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static void
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rmi_pci_bus_space_read_multi_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int8_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_multi_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_multi_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int32_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_region_1(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_region_2(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_region_4(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, u_int32_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int8_t value);
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static void
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rmi_pci_bus_space_write_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int16_t value);
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static void
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rmi_pci_bus_space_write_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int32_t value);
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static void
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rmi_pci_bus_space_write_multi_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int8_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_multi_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_multi_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int32_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_region_2(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset,
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const u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_region_4(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset,
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const u_int32_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_set_region_2(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, u_int16_t value,
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size_t count);
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static void
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rmi_pci_bus_space_set_region_4(void *t,
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bus_space_handle_t bsh,
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bus_size_t offset, u_int32_t value,
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size_t count);
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static void
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rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
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bus_size_t offset __unused, bus_size_t len __unused, int flags);
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static void
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rmi_pci_bus_space_copy_region_2(void *t,
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bus_space_handle_t bsh1,
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bus_size_t off1,
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bus_space_handle_t bsh2,
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bus_size_t off2, size_t count);
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u_int8_t
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rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
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bus_size_t offset);
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static u_int16_t
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rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
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bus_size_t offset);
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static u_int32_t
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rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
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bus_size_t offset);
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static void
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rmi_pci_bus_space_read_multi_stream_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int8_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_multi_stream_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_read_multi_stream_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset, u_int32_t * addr,
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size_t count);
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void
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rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
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bus_size_t offset, u_int8_t value);
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static void
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rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
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bus_size_t offset, u_int16_t value);
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static void
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rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
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bus_size_t offset, u_int32_t value);
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static void
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rmi_pci_bus_space_write_multi_stream_1(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int8_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_multi_stream_2(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int16_t * addr,
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size_t count);
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static void
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rmi_pci_bus_space_write_multi_stream_4(void *t,
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bus_space_handle_t handle,
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bus_size_t offset,
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const u_int32_t * addr,
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size_t count);
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#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
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static struct bus_space local_rmi_pci_bus_space = {
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/* cookie */
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(void *)0,
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/* mapping/unmapping */
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rmi_pci_bus_space_map,
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rmi_pci_bus_space_unmap,
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rmi_pci_bus_space_subregion,
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/* allocation/deallocation */
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NULL,
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NULL,
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/* barrier */
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rmi_pci_bus_space_barrier,
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/* read (single) */
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rmi_pci_bus_space_read_1,
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rmi_pci_bus_space_read_2,
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rmi_pci_bus_space_read_4,
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NULL,
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/* read multiple */
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rmi_pci_bus_space_read_multi_1,
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rmi_pci_bus_space_read_multi_2,
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rmi_pci_bus_space_read_multi_4,
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NULL,
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/* read region */
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rmi_pci_bus_space_read_region_1,
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rmi_pci_bus_space_read_region_2,
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rmi_pci_bus_space_read_region_4,
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NULL,
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/* write (single) */
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rmi_pci_bus_space_write_1,
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rmi_pci_bus_space_write_2,
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rmi_pci_bus_space_write_4,
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NULL,
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/* write multiple */
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rmi_pci_bus_space_write_multi_1,
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rmi_pci_bus_space_write_multi_2,
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rmi_pci_bus_space_write_multi_4,
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NULL,
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/* write region */
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NULL,
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rmi_pci_bus_space_write_region_2,
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rmi_pci_bus_space_write_region_4,
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NULL,
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/* set multiple */
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NULL,
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NULL,
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NULL,
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NULL,
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/* set region */
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NULL,
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rmi_pci_bus_space_set_region_2,
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rmi_pci_bus_space_set_region_4,
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NULL,
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/* copy */
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NULL,
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rmi_pci_bus_space_copy_region_2,
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NULL,
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NULL,
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/* read (single) stream */
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rmi_pci_bus_space_read_stream_1,
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rmi_pci_bus_space_read_stream_2,
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rmi_pci_bus_space_read_stream_4,
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NULL,
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/* read multiple stream */
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rmi_pci_bus_space_read_multi_stream_1,
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rmi_pci_bus_space_read_multi_stream_2,
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rmi_pci_bus_space_read_multi_stream_4,
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NULL,
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/* read region stream */
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rmi_pci_bus_space_read_region_1,
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rmi_pci_bus_space_read_region_2,
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rmi_pci_bus_space_read_region_4,
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NULL,
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/* write (single) stream */
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rmi_pci_bus_space_write_stream_1,
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rmi_pci_bus_space_write_stream_2,
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rmi_pci_bus_space_write_stream_4,
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NULL,
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/* write multiple stream */
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rmi_pci_bus_space_write_multi_stream_1,
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rmi_pci_bus_space_write_multi_stream_2,
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rmi_pci_bus_space_write_multi_stream_4,
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NULL,
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/* write region stream */
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NULL,
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rmi_pci_bus_space_write_region_2,
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rmi_pci_bus_space_write_region_4,
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NULL,
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};
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/* generic bus_space tag */
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bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space;
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/*
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* Map a region of device bus space into CPU virtual address space.
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*/
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static int
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rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr,
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bus_size_t size __unused, int flags __unused,
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bus_space_handle_t * bshp)
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{
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*bshp = addr;
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return (0);
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}
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/*
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* Unmap a region of device bus space.
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*/
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static void
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rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
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bus_size_t size __unused)
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{
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}
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/*
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* Get a new handle for a subregion of an already-mapped area of bus space.
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*/
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static int
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rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
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bus_size_t offset, bus_size_t size __unused,
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bus_space_handle_t * nbshp)
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{
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*nbshp = bsh + offset;
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return (0);
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}
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/*
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* Read a 1, 2, 4, or 8 byte quantity from bus space
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* described by tag/handle/offset.
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*/
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static u_int8_t
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rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return (u_int8_t) (*(volatile u_int8_t *)(handle + offset));
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}
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static u_int16_t
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rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return bswap16((u_int16_t) (*(volatile u_int16_t *)(handle + offset)));
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}
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static u_int32_t
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rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle,
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bus_size_t offset)
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{
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return bswap32((*(volatile u_int32_t *)(handle + offset)));
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}
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/*
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* Read `count' 1, 2, 4, or 8 byte quantities from bus space
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* described by tag/handle/offset and copy into buffer provided.
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*/
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static void
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rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
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bus_size_t offset, u_int8_t * addr, size_t count)
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{
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while (count--) {
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*addr = (*(volatile u_int8_t *)(handle + offset));
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addr++;
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}
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}
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static void
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rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
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bus_size_t offset, u_int16_t * addr, size_t count)
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{
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while (count--) {
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*addr = *(volatile u_int16_t *)(handle + offset);
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*addr = bswap16(*addr);
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addr++;
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}
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}
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static void
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rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
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bus_size_t offset, u_int32_t * addr, size_t count)
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{
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while (count--) {
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*addr = *(volatile u_int32_t *)(handle + offset);
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*addr = bswap32(*addr);
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addr++;
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}
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}
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/*
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* Write the 1, 2, 4, or 8 byte value `value' to bus space
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* described by tag/handle/offset.
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*/
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static void
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rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle,
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bus_size_t offset, u_int8_t value)
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{
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mips_sync();
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*(volatile u_int8_t *)(handle + offset) = value;
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}
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static void
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rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle,
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bus_size_t offset, u_int16_t value)
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{
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mips_sync();
|
||||
*(volatile u_int16_t *)(handle + offset) = bswap16(value);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int32_t value)
|
||||
{
|
||||
mips_sync();
|
||||
*(volatile u_int32_t *)(handle + offset) = bswap32(value);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
|
||||
* provided to bus space described by tag/handle/offset.
|
||||
*/
|
||||
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int8_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int8_t *)(handle + offset)) = *addr;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int16_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int32_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr);
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
|
||||
* by tag/handle starting at `offset'.
|
||||
*/
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, u_int16_t value, size_t count)
|
||||
{
|
||||
bus_addr_t addr = bsh + offset;
|
||||
|
||||
for (; count != 0; count--, addr += 2)
|
||||
(*(volatile u_int16_t *)(addr)) = value;
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, u_int32_t value, size_t count)
|
||||
{
|
||||
bus_addr_t addr = bsh + offset;
|
||||
|
||||
for (; count != 0; count--, addr += 4)
|
||||
(*(volatile u_int32_t *)(addr)) = value;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
|
||||
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
|
||||
*/
|
||||
static void
|
||||
rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
|
||||
bus_size_t off1, bus_space_handle_t bsh2,
|
||||
bus_size_t off2, size_t count)
|
||||
{
|
||||
TODO();
|
||||
}
|
||||
|
||||
/*
|
||||
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
|
||||
* described by tag/handle/offset and copy into buffer provided.
|
||||
*/
|
||||
|
||||
u_int8_t
|
||||
rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset)
|
||||
{
|
||||
|
||||
return *((volatile u_int8_t *)(handle + offset));
|
||||
}
|
||||
|
||||
|
||||
static u_int16_t
|
||||
rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset)
|
||||
{
|
||||
return *(volatile u_int16_t *)(handle + offset);
|
||||
}
|
||||
|
||||
|
||||
static u_int32_t
|
||||
rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset)
|
||||
{
|
||||
return (*(volatile u_int32_t *)(handle + offset));
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int8_t * addr, size_t count)
|
||||
{
|
||||
while (count--) {
|
||||
*addr = (*(volatile u_int8_t *)(handle + offset));
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int16_t * addr, size_t count)
|
||||
{
|
||||
while (count--) {
|
||||
*addr = (*(volatile u_int16_t *)(handle + offset));
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int32_t * addr, size_t count)
|
||||
{
|
||||
while (count--) {
|
||||
*addr = (*(volatile u_int32_t *)(handle + offset));
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
|
||||
* described by tag/handle and starting at `offset' and copy into
|
||||
* buffer provided.
|
||||
*/
|
||||
void
|
||||
rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, u_int8_t * addr, size_t count)
|
||||
{
|
||||
bus_addr_t baddr = bsh + offset;
|
||||
|
||||
while (count--) {
|
||||
*addr++ = (*(volatile u_int8_t *)(baddr));
|
||||
baddr += 1;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, u_int16_t * addr, size_t count)
|
||||
{
|
||||
bus_addr_t baddr = bsh + offset;
|
||||
|
||||
while (count--) {
|
||||
*addr++ = (*(volatile u_int16_t *)(baddr));
|
||||
baddr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, u_int32_t * addr, size_t count)
|
||||
{
|
||||
bus_addr_t baddr = bsh + offset;
|
||||
|
||||
while (count--) {
|
||||
*addr++ = (*(volatile u_int32_t *)(baddr));
|
||||
baddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int8_t value)
|
||||
{
|
||||
mips_sync();
|
||||
*(volatile u_int8_t *)(handle + offset) = value;
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int16_t value)
|
||||
{
|
||||
mips_sync();
|
||||
*(volatile u_int16_t *)(handle + offset) = value;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
|
||||
bus_size_t offset, u_int32_t value)
|
||||
{
|
||||
mips_sync();
|
||||
*(volatile u_int32_t *)(handle + offset) = value;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int8_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int8_t *)(handle + offset)) = *addr;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int16_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int16_t *)(handle + offset)) = *addr;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
|
||||
bus_size_t offset, const u_int32_t * addr, size_t count)
|
||||
{
|
||||
mips_sync();
|
||||
while (count--) {
|
||||
(*(volatile u_int32_t *)(handle + offset)) = *addr;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
rmi_pci_bus_space_write_region_2(void *t,
|
||||
bus_space_handle_t bsh,
|
||||
bus_size_t offset,
|
||||
const u_int16_t * addr,
|
||||
size_t count)
|
||||
{
|
||||
bus_addr_t baddr = (bus_addr_t) bsh + offset;
|
||||
|
||||
while (count--) {
|
||||
(*(volatile u_int16_t *)(baddr)) = *addr;
|
||||
addr++;
|
||||
baddr += 2;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
|
||||
bus_size_t offset, const u_int32_t * addr, size_t count)
|
||||
{
|
||||
bus_addr_t baddr = bsh + offset;
|
||||
|
||||
while (count--) {
|
||||
(*(volatile u_int32_t *)(baddr)) = *addr;
|
||||
addr++;
|
||||
baddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
|
||||
bus_size_t offset __unused, bus_size_t len __unused, int flags)
|
||||
{
|
||||
|
||||
}
|
||||
/*-
|
||||
* Copyright (c) 2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
|
||||
@ -14,10 +14,10 @@ mips/rmi/uart_bus_xlr_iodi.c optional uart
|
||||
mips/rmi/uart_cpu_mips_xlr.c optional uart
|
||||
mips/rmi/perfmon_kern.c optional xlr_perfmon
|
||||
mips/rmi/perfmon_percpu.c optional xlr_perfmon
|
||||
#mips/rmi/pcibus.c optional pci
|
||||
#mips/rmi/xlr_pci.c optional pci
|
||||
mips/rmi/xlr_pci.c optional pci
|
||||
#mips/rmi/xls_ehci.c optional usb ehci
|
||||
mips/rmi/bus_space_rmi.c standard
|
||||
mips/rmi/bus_space_rmi_pci.c optional pci
|
||||
mips/rmi/dev/sec/rmisec.c optional rmisec
|
||||
mips/rmi/dev/sec/rmilib.c optional rmisec
|
||||
mips/rmi/dev/xlr/rge.c optional rge
|
||||
|
||||
@ -25,38 +25,11 @@
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
#define DEFAULT_PCI_CONFIG_BASE 0x18000000
|
||||
#define DEFAULT_PCI_CONFIG_BASE 0x18000000
|
||||
#define MSI_MIPS_ADDR_BASE 0xfee00000
|
||||
|
||||
#define MSI_MIPS_ADDR_BASE 0xfee00000
|
||||
#define PCIE_LINK0_MSI_STATUS 0x90
|
||||
#define PCIE_LINK1_MSI_STATUS 0x94
|
||||
#define PCIE_LINK2_MSI_STATUS 0x190
|
||||
#define PCIE_LINK3_MSI_STATUS 0x194
|
||||
|
||||
|
||||
#define PCIE_LINK0_MSI_STATUS 0x90
|
||||
#define PCIE_LINK1_MSI_STATUS 0x94
|
||||
#define PCIE_LINK2_MSI_STATUS 0x190
|
||||
#define PCIE_LINK3_MSI_STATUS 0x194
|
||||
|
||||
void pci_init_resources(void);
|
||||
struct resource *
|
||||
xlr_pci_alloc_resource(device_t bus, device_t child,
|
||||
int type, int *rid,
|
||||
u_long start, u_long end, u_long count,
|
||||
u_int flags);
|
||||
int
|
||||
pci_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
int
|
||||
pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
int
|
||||
pci_release_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r);
|
||||
struct rman *pci_get_rman(device_t dev, int type);
|
||||
|
||||
int
|
||||
mips_platform_pci_setup_intr(device_t dev, device_t child,
|
||||
struct resource *irq, int flags,
|
||||
driver_filter_t * filt,
|
||||
driver_intr_t * intr, void *arg,
|
||||
void **cookiep);
|
||||
int
|
||||
mips_pci_route_interrupt(device_t bus, device_t dev, int pin);
|
||||
|
||||
@ -28,17 +28,21 @@
|
||||
*
|
||||
* RMI_BSD */
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/endian.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/md_var.h>
|
||||
#include <machine/intr_machdep.h>
|
||||
#include <mips/rmi/rmi_mips_exts.h>
|
||||
#include <mips/rmi/interrupt.h>
|
||||
#include <machine/cpuregs.h>
|
||||
#include <vm/vm.h>
|
||||
#include <vm/vm_param.h>
|
||||
@ -47,50 +51,46 @@
|
||||
#include <sys/rman.h>
|
||||
#include <dev/pci/pcivar.h>
|
||||
#include <dev/pci/pcireg.h>
|
||||
#include <dev/pci/pcib_private.h>
|
||||
|
||||
#include <mips/rmi/iomap.h>
|
||||
#include <mips/rmi/pic.h>
|
||||
#include <mips/rmi/shared_structs.h>
|
||||
#include <mips/rmi/board.h>
|
||||
#include <mips/rmi/pcibus.h>
|
||||
|
||||
#include "pcib_if.h"
|
||||
|
||||
#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
|
||||
#define PCIE_LINK_STATE 0x4000
|
||||
|
||||
#define LSU_CFG0_REGID 0
|
||||
#define LSU_CERRLOG_REGID 9
|
||||
#define LSU_CERROVF_REGID 10
|
||||
#define LSU_CERRINT_REGID 11
|
||||
#define SWAP32(x)\
|
||||
(((x) & 0xff000000) >> 24) | \
|
||||
(((x) & 0x000000ff) << 24) | \
|
||||
(((x) & 0x0000ff00) << 8) | \
|
||||
(((x) & 0x00ff0000) >> 8)
|
||||
|
||||
|
||||
/* MSI support */
|
||||
|
||||
#define MSI_MIPS_ADDR_DEST 0x000ff000
|
||||
#define MSI_MIPS_ADDR_RH 0x00000008
|
||||
#define MSI_MIPS_ADDR_RH_OFF 0x00000000
|
||||
#define MSI_MIPS_ADDR_RH_ON 0x00000008
|
||||
#define MSI_MIPS_ADDR_DM 0x00000004
|
||||
#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
|
||||
#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
|
||||
#define MSI_MIPS_ADDR_DEST 0x000ff000
|
||||
#define MSI_MIPS_ADDR_RH 0x00000008
|
||||
#define MSI_MIPS_ADDR_RH_OFF 0x00000000
|
||||
#define MSI_MIPS_ADDR_RH_ON 0x00000008
|
||||
#define MSI_MIPS_ADDR_DM 0x00000004
|
||||
#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
|
||||
#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
|
||||
|
||||
/* Fields in data for Intel MSI messages. */
|
||||
#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
|
||||
#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
|
||||
#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
|
||||
#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
|
||||
#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
|
||||
#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
|
||||
|
||||
#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
|
||||
#define MSI_MIPS_DATA_DEASSERT 0x00000000
|
||||
#define MSI_MIPS_DATA_ASSERT 0x00004000
|
||||
#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
|
||||
#define MSI_MIPS_DATA_DEASSERT 0x00000000
|
||||
#define MSI_MIPS_DATA_ASSERT 0x00004000
|
||||
|
||||
#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
|
||||
#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
|
||||
#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
|
||||
#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
|
||||
#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
|
||||
#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
|
||||
|
||||
#define MSI_MIPS_DATA_INTVEC 0x000000ff
|
||||
#define MSI_MIPS_DATA_INTVEC 0x000000ff
|
||||
|
||||
/*
|
||||
* Build Intel MSI message and data values from a source. AMD64 systems
|
||||
@ -104,53 +104,96 @@
|
||||
(MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
|
||||
MSI_MIPS_DATA_ASSERT | (irq))
|
||||
|
||||
struct xlr_hose_softc {
|
||||
#define DEBUG
|
||||
#ifdef DEBUG
|
||||
#define dbg_devprintf device_printf
|
||||
#else
|
||||
#define dbg_devprintf(dev, fmt, ...)
|
||||
#endif
|
||||
|
||||
struct xlr_pcib_softc {
|
||||
int junk; /* no softc */
|
||||
};
|
||||
static devclass_t pcib_devclass;
|
||||
static int pci_bus_status = 0;
|
||||
static void *pci_config_base;
|
||||
|
||||
static uint32_t pci_cfg_read_32bit(uint32_t addr);
|
||||
static void pci_cfg_write_32bit(uint32_t addr, uint32_t data);
|
||||
extern bus_space_tag_t rmi_pci_bus_space;
|
||||
static devclass_t pcib_devclass;
|
||||
static void *xlr_pci_config_base;
|
||||
static struct rman irq_rman, port_rman, mem_rman;
|
||||
|
||||
static void
|
||||
xlr_pci_init_resources(void)
|
||||
{
|
||||
irq_rman.rm_start = 0;
|
||||
irq_rman.rm_end = 255;
|
||||
irq_rman.rm_type = RMAN_ARRAY;
|
||||
irq_rman.rm_descr = "PCI Mapped Interrupts";
|
||||
if (rman_init(&irq_rman)
|
||||
|| rman_manage_region(&irq_rman, 0, 255))
|
||||
panic("pci_init_resources irq_rman");
|
||||
|
||||
port_rman.rm_start = 0;
|
||||
port_rman.rm_end = ~0u;
|
||||
port_rman.rm_type = RMAN_ARRAY;
|
||||
port_rman.rm_descr = "I/O ports";
|
||||
if (rman_init(&port_rman)
|
||||
|| rman_manage_region(&port_rman, 0x10000000, 0x1fffffff))
|
||||
panic("pci_init_resources port_rman");
|
||||
|
||||
mem_rman.rm_start = 0;
|
||||
mem_rman.rm_end = ~0u;
|
||||
mem_rman.rm_type = RMAN_ARRAY;
|
||||
mem_rman.rm_descr = "I/O memory";
|
||||
if (rman_init(&mem_rman)
|
||||
|| rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff))
|
||||
panic("pci_init_resources mem_rman");
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pcib_probe(device_t dev)
|
||||
{
|
||||
device_set_desc(dev, "xlr system bridge controller");
|
||||
if (xlr_board_info.is_xls)
|
||||
device_set_desc(dev, "XLS PCIe bus");
|
||||
else
|
||||
device_set_desc(dev, "XLR PCI bus");
|
||||
|
||||
pci_init_resources();
|
||||
pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
|
||||
pci_bus_status = 1;
|
||||
xlr_pci_init_resources();
|
||||
xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t * result)
|
||||
xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
|
||||
{
|
||||
#if 0
|
||||
device_printf(dev, "xlr_pcib_read_ivar : read ivar %d for child %s\n", which, device_get_nameunit(child));
|
||||
#endif
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
*result = 0;
|
||||
return (0);
|
||||
case PCIB_IVAR_BUS:
|
||||
*result = 0;
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
return ENOENT;
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
|
||||
{
|
||||
switch (which) {
|
||||
case PCIB_IVAR_DOMAIN:
|
||||
return (EINVAL);
|
||||
case PCIB_IVAR_BUS:
|
||||
return (EINVAL);
|
||||
}
|
||||
return (ENOENT);
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pcib_maxslots(device_t dev)
|
||||
{
|
||||
if (xlr_board_info.is_xls)
|
||||
return 4;
|
||||
else
|
||||
return 32;
|
||||
return (PCI_SLOTMAX);
|
||||
}
|
||||
|
||||
#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
|
||||
|
||||
static __inline__ void
|
||||
disable_and_clear_cache_error(void)
|
||||
{
|
||||
@ -178,8 +221,29 @@ clear_and_enable_cache_error(void)
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
phoenix_pciread(u_int b, u_int s, u_int f,
|
||||
u_int reg, int width)
|
||||
pci_cfg_read_32bit(uint32_t addr)
|
||||
{
|
||||
uint32_t temp = 0;
|
||||
uint32_t *p = (uint32_t *) ((uint32_t) xlr_pci_config_base + (addr & ~3));
|
||||
uint64_t cerr_cpu_log = 0;
|
||||
|
||||
disable_and_clear_cache_error();
|
||||
|
||||
temp = bswap32(*p);
|
||||
|
||||
/* Read cache err log */
|
||||
cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
|
||||
if (cerr_cpu_log) {
|
||||
/* Device don't exist. */
|
||||
temp = ~0x0;
|
||||
}
|
||||
clear_and_enable_cache_error();
|
||||
return temp;
|
||||
}
|
||||
|
||||
static u_int32_t
|
||||
xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
|
||||
u_int reg, int width)
|
||||
{
|
||||
uint32_t data = 0;
|
||||
|
||||
@ -188,10 +252,7 @@ phoenix_pciread(u_int b, u_int s, u_int f,
|
||||
else if ((width == 4) && (reg & 3))
|
||||
return 0xFFFFFFFF;
|
||||
|
||||
if (pci_bus_status)
|
||||
data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
|
||||
else
|
||||
data = 0xFFFFFFFF;
|
||||
data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
|
||||
|
||||
if (width == 1)
|
||||
return ((data >> ((reg & 3) << 3)) & 0xff);
|
||||
@ -201,21 +262,18 @@ phoenix_pciread(u_int b, u_int s, u_int f,
|
||||
return data;
|
||||
}
|
||||
|
||||
static void
|
||||
phoenix_pciwrite(u_int b, u_int s, u_int f,
|
||||
u_int reg, u_int val, int width)
|
||||
static void
|
||||
xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
|
||||
u_int reg, u_int32_t val, int width)
|
||||
{
|
||||
uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
|
||||
uint32_t data = 0;
|
||||
uint32_t data = 0, *p;
|
||||
|
||||
if ((width == 2) && (reg & 1))
|
||||
return;
|
||||
else if ((width == 4) && (reg & 3))
|
||||
return;
|
||||
|
||||
if (!pci_bus_status)
|
||||
return;
|
||||
|
||||
if (width == 1) {
|
||||
data = pci_cfg_read_32bit(cfgaddr);
|
||||
data = (data & ~(0xff << ((reg & 3) << 3))) |
|
||||
@ -228,56 +286,12 @@ phoenix_pciwrite(u_int b, u_int s, u_int f,
|
||||
data = val;
|
||||
}
|
||||
|
||||
pci_cfg_write_32bit(cfgaddr, data);
|
||||
p = (uint32_t *)((uint32_t) xlr_pci_config_base + (cfgaddr & ~3));
|
||||
*p = bswap32(data);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
pci_cfg_read_32bit(uint32_t addr)
|
||||
{
|
||||
uint32_t temp = 0;
|
||||
uint32_t *p = (uint32_t *) ((uint32_t) pci_config_base + (addr & ~3));
|
||||
uint64_t cerr_cpu_log = 0;
|
||||
|
||||
disable_and_clear_cache_error();
|
||||
|
||||
temp = SWAP32(*p);
|
||||
|
||||
/* Read cache err log */
|
||||
cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
|
||||
|
||||
if (cerr_cpu_log) {
|
||||
/* Device don't exist. */
|
||||
temp = ~0x0;
|
||||
}
|
||||
clear_and_enable_cache_error();
|
||||
return temp;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
pci_cfg_write_32bit(uint32_t addr, uint32_t data)
|
||||
{
|
||||
unsigned int *p = (unsigned int *)((uint32_t) pci_config_base + (addr & ~3));
|
||||
|
||||
*p = SWAP32(data);
|
||||
}
|
||||
|
||||
static u_int32_t
|
||||
xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
|
||||
u_int reg, int width)
|
||||
{
|
||||
return phoenix_pciread(b, s, f, reg, width);
|
||||
}
|
||||
|
||||
static void
|
||||
xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
|
||||
u_int reg, u_int32_t val, int width)
|
||||
{
|
||||
phoenix_pciwrite(b, s, f, reg, val, width);
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pcib_attach(device_t dev)
|
||||
{
|
||||
@ -286,28 +300,24 @@ xlr_pcib_attach(device_t dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PCIE_LINK_STATE 0x4000
|
||||
|
||||
static void
|
||||
xlr_pcib_identify(driver_t * driver, device_t parent)
|
||||
{
|
||||
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
|
||||
xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
|
||||
xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
|
||||
if (xlr_board_info.is_xls) {
|
||||
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
|
||||
xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
|
||||
xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
|
||||
|
||||
if ((uint16_t) reg_link0 & PCIE_LINK_STATE) {
|
||||
device_printf(parent, "Link 0 up\n");
|
||||
}
|
||||
if ((uint16_t) reg_link1 & PCIE_LINK_STATE) {
|
||||
device_printf(parent, "Link 1 up\n");
|
||||
if ((uint16_t) reg_link0 & PCIE_LINK_STATE) {
|
||||
device_printf(parent, "Link 0 up\n");
|
||||
}
|
||||
if ((uint16_t) reg_link1 & PCIE_LINK_STATE) {
|
||||
device_printf(parent, "Link 1 up\n");
|
||||
}
|
||||
}
|
||||
|
||||
BUS_ADD_CHILD(parent, 0, "pcib", 0);
|
||||
|
||||
}
|
||||
static int
|
||||
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
|
||||
static int
|
||||
xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs);
|
||||
|
||||
static int
|
||||
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
|
||||
@ -364,8 +374,6 @@ xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
|
||||
device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib), count);
|
||||
return 0;
|
||||
}
|
||||
static int
|
||||
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data);
|
||||
|
||||
static int
|
||||
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data)
|
||||
@ -387,6 +395,212 @@ xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * da
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
bridge_pcix_ack(void *arg)
|
||||
{
|
||||
xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
|
||||
}
|
||||
|
||||
static void
|
||||
bridge_pcix_mask_ack(void *arg)
|
||||
{
|
||||
xlr_mask_hard_irq(arg);
|
||||
bridge_pcix_ack(arg);
|
||||
}
|
||||
|
||||
static void
|
||||
bridge_pcie_ack(void *arg)
|
||||
{
|
||||
int irq = (int)arg;
|
||||
uint32_t reg;
|
||||
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
|
||||
|
||||
switch (irq) {
|
||||
case PIC_PCIE_LINK0_IRQ : reg = PCIE_LINK0_MSI_STATUS; break;
|
||||
case PIC_PCIE_LINK1_IRQ : reg = PCIE_LINK1_MSI_STATUS; break;
|
||||
case PIC_PCIE_LINK2_IRQ : reg = PCIE_LINK2_MSI_STATUS; break;
|
||||
case PIC_PCIE_LINK3_IRQ : reg = PCIE_LINK3_MSI_STATUS; break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
|
||||
}
|
||||
|
||||
static void
|
||||
bridge_pcie_mask_ack(void *arg)
|
||||
{
|
||||
xlr_mask_hard_irq(arg);
|
||||
bridge_pcie_ack(arg);
|
||||
}
|
||||
|
||||
static int
|
||||
mips_platform_pci_setup_intr(device_t dev, device_t child,
|
||||
struct resource *irq, int flags,
|
||||
driver_filter_t * filt,
|
||||
driver_intr_t * intr, void *arg,
|
||||
void **cookiep)
|
||||
{
|
||||
int level;
|
||||
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
|
||||
int error = 0;
|
||||
int xlrirq;
|
||||
|
||||
error = rman_activate_resource(irq);
|
||||
if (error)
|
||||
return error;
|
||||
if (rman_get_start(irq) != rman_get_end(irq)) {
|
||||
device_printf(dev, "Interrupt allocation %lu != %lu\n",
|
||||
rman_get_start(irq), rman_get_end(irq));
|
||||
return EINVAL;
|
||||
}
|
||||
xlrirq = rman_get_start(irq);
|
||||
|
||||
if (strcmp(device_get_name(dev), "pcib") != 0)
|
||||
return 0;
|
||||
|
||||
if (xlr_board_info.is_xls == 0) {
|
||||
if (rmi_spin_mutex_safe)
|
||||
mtx_lock_spin(&xlr_pic_lock);
|
||||
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
|
||||
xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
|
||||
xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
|
||||
(1 << 6) | (PIC_PCIX_IRQ)));
|
||||
if (rmi_spin_mutex_safe)
|
||||
mtx_unlock_spin(&xlr_pic_lock);
|
||||
xlr_cpu_establish_hardintr(device_get_name(child), filt,
|
||||
intr, arg, PIC_PCIX_IRQ, flags, cookiep,
|
||||
bridge_pcix_mask_ack, xlr_unmask_hard_irq,
|
||||
bridge_pcix_ack, NULL);
|
||||
} else {
|
||||
if (rmi_spin_mutex_safe)
|
||||
mtx_lock_spin(&xlr_pic_lock);
|
||||
xlr_write_reg(mmio, PIC_IRT_0_BASE + xlrirq - PIC_IRQ_BASE, 0x01);
|
||||
xlr_write_reg(mmio, PIC_IRT_1_BASE + xlrirq - PIC_IRQ_BASE,
|
||||
((1 << 31) | (1 << 30) | (1 << 6) | xlrirq));
|
||||
if (rmi_spin_mutex_safe)
|
||||
mtx_unlock_spin(&xlr_pic_lock);
|
||||
|
||||
xlr_cpu_establish_hardintr(device_get_name(child), filt,
|
||||
intr, arg, xlrirq, flags, cookiep,
|
||||
bridge_pcie_mask_ack, xlr_unmask_hard_irq,
|
||||
bridge_pcie_ack, NULL);
|
||||
}
|
||||
|
||||
return bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
|
||||
arg, cookiep);
|
||||
}
|
||||
|
||||
static int
|
||||
mips_platform_pci_teardown_intr(device_t dev, device_t child,
|
||||
struct resource *irq, void *cookie)
|
||||
{
|
||||
if (strcmp(device_get_name(child), "pci") == 0) {
|
||||
/* if needed reprogram the pic to clear pcix related entry */
|
||||
device_printf(dev, "teardown intr\n");
|
||||
}
|
||||
return bus_generic_teardown_intr(dev, child, irq, cookie);
|
||||
}
|
||||
|
||||
static struct resource *
|
||||
xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct rman *rm;
|
||||
struct resource *rv;
|
||||
vm_offset_t va;
|
||||
int needactivate = flags & RF_ACTIVE;
|
||||
|
||||
switch (type) {
|
||||
case SYS_RES_IRQ:
|
||||
rm = &irq_rman;
|
||||
break;
|
||||
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &port_rman;
|
||||
break;
|
||||
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &mem_rman;
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
rv = rman_reserve_resource(rm, start, end, count, flags, child);
|
||||
if (rv == 0)
|
||||
return 0;
|
||||
|
||||
rman_set_rid(rv, *rid);
|
||||
|
||||
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
|
||||
va = (vm_offset_t)pmap_mapdev(start, count);
|
||||
rman_set_bushandle(rv, va);
|
||||
/* bushandle is same as virtual addr */
|
||||
rman_set_virtual(rv, (void *)va);
|
||||
rman_set_bustag(rv, rmi_pci_bus_space);
|
||||
}
|
||||
|
||||
if (needactivate) {
|
||||
if (bus_activate_resource(child, type, *rid, rv)) {
|
||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pci_release_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
return (rman_release_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
return (rman_activate_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
|
||||
struct resource *r)
|
||||
{
|
||||
return (rman_deactivate_resource(r));
|
||||
}
|
||||
|
||||
static int
|
||||
mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
|
||||
{
|
||||
/*
|
||||
* Validate requested pin number.
|
||||
*/
|
||||
if ((pin < 1) || (pin > 4))
|
||||
return (255);
|
||||
|
||||
if (xlr_board_info.is_xls) {
|
||||
switch (pin) {
|
||||
case 1:
|
||||
return PIC_PCIE_LINK0_IRQ;
|
||||
case 2:
|
||||
return PIC_PCIE_LINK1_IRQ;
|
||||
case 3:
|
||||
return PIC_PCIE_LINK2_IRQ;
|
||||
case 4:
|
||||
return PIC_PCIE_LINK3_IRQ;
|
||||
}
|
||||
} else {
|
||||
if (pin == 1) {
|
||||
return (16);
|
||||
}
|
||||
}
|
||||
|
||||
return (255);
|
||||
}
|
||||
|
||||
static device_method_t xlr_pcib_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_identify, xlr_pcib_identify),
|
||||
@ -396,18 +610,18 @@ static device_method_t xlr_pcib_methods[] = {
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
||||
DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, xlr_pcib_write_ivar),
|
||||
DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, pci_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, pci_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
|
||||
DEVMETHOD(bus_release_resource, xlr_pci_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, xlr_pci_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, xlr_pci_deactivate_resource),
|
||||
DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
||||
DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr),
|
||||
|
||||
/* pcib interface */
|
||||
DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
|
||||
DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
|
||||
DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
|
||||
|
||||
DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
|
||||
|
||||
DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
|
||||
@ -420,7 +634,7 @@ static device_method_t xlr_pcib_methods[] = {
|
||||
static driver_t xlr_pcib_driver = {
|
||||
"pcib",
|
||||
xlr_pcib_methods,
|
||||
sizeof(struct xlr_hose_softc),
|
||||
sizeof(struct xlr_pcib_softc),
|
||||
};
|
||||
|
||||
DRIVER_MODULE(pcib, nexus, xlr_pcib_driver, pcib_devclass, 0, 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user