Improve ARM debug_monitor for SMP machines
- Reset debug architecture and enable monitor for secondary CPUs in init_secondary() rather than when configuring watchpoint, etc. - Disable HW debugging capabilities when one of the CPU cores fails to set up. - Use dbg_capable() in a more atomic manner to avoid any mismatch between CPUs. Differential Revision: https://reviews.freebsd.org/D6009
This commit is contained in:
Zbigniew Bodek
parent
9ae1207bcf
commit
01ed3219b9
@ -72,9 +72,8 @@ static boolean_t dbg_check_slot_free(enum dbg_t, u_int);
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static int dbg_remove_xpoint(struct dbg_wb_conf *);
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static int dbg_setup_xpoint(struct dbg_wb_conf *);
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static boolean_t dbg_capable; /* Indicates that machine is capable of using
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static int dbg_capable_var; /* Indicates that machine is capable of using
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HW watchpoints/breakpoints */
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static boolean_t dbg_ready[MAXCPU]; /* Debug arch. reset performed on this CPU */
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static uint32_t dbg_model; /* Debug Arch. Model */
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static boolean_t dbg_ossr; /* OS Save and Restore implemented */
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@ -245,6 +244,13 @@ dbg_wb_write_reg(int reg, int n, uint32_t val)
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isb();
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}
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static __inline boolean_t
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dbg_capable(void)
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{
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return (atomic_cmpset_int(&dbg_capable_var, 0, 0) == 0);
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}
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boolean_t
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kdb_cpu_pc_is_singlestep(db_addr_t pc)
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{
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@ -253,7 +259,7 @@ kdb_cpu_pc_is_singlestep(db_addr_t pc)
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* there will be no stepping capabilities
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* (SOFTWARE_SSTEP is not defined for __ARM_ARCH >= 6).
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*/
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if (!dbg_capable)
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if (!dbg_capable())
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return (FALSE);
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if (dbg_find_slot(DBG_TYPE_BREAKPOINT, pc) != ~0U)
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@ -270,7 +276,7 @@ kdb_cpu_set_singlestep(void)
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uint32_t wcr;
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u_int i;
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if (!dbg_capable)
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if (!dbg_capable())
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return;
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/*
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@ -303,7 +309,7 @@ kdb_cpu_clear_singlestep(void)
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uint32_t wvr, wcr;
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u_int i;
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if (!dbg_capable)
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if (!dbg_capable())
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return;
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dbg_remove_breakpoint(DBG_BKPT_BT_SLOT);
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@ -423,7 +429,7 @@ dbg_show_watchpoint(void)
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boolean_t is_enabled;
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int i;
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if (!dbg_capable) {
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if (!dbg_capable()) {
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db_printf("Architecture does not support HW "
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"breakpoints/watchpoints\n");
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return;
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@ -591,24 +597,15 @@ dbg_setup_xpoint(struct dbg_wb_conf *conf)
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uint32_t cr_size, cr_priv, cr_access;
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uint32_t reg_ctrl, reg_addr, ctrl, addr;
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boolean_t is_bkpt;
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u_int cpuid, cpu;
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u_int cpu;
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u_int i;
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int err;
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if (!dbg_capable)
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if (!dbg_capable())
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return (ENXIO);
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is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
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typestr = is_bkpt ? "breakpoint" : "watchpoint";
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cpuid = PCPU_GET(cpuid);
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if (!dbg_ready[cpuid]) {
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err = dbg_reset_state();
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if (err != 0)
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return (err);
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dbg_ready[cpuid] = TRUE;
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}
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if (is_bkpt) {
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if (dbg_breakpoint_num == 0) {
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db_printf("Breakpoints not supported on this architecture\n");
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@ -698,7 +695,7 @@ dbg_setup_xpoint(struct dbg_wb_conf *conf)
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d->dbg_wvr[i] = addr;
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d->dbg_wcr[i] = ctrl;
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/* Skip update command for the current CPU */
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if (cpu != cpuid)
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if (cpu != PCPU_GET(cpuid))
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pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
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}
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}
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@ -715,23 +712,13 @@ dbg_remove_xpoint(struct dbg_wb_conf *conf)
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struct dbreg *d;
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uint32_t reg_ctrl, reg_addr, addr;
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boolean_t is_bkpt;
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u_int cpuid, cpu;
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u_int cpu;
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u_int i;
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int err;
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if (!dbg_capable)
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if (!dbg_capable())
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return (ENXIO);
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is_bkpt = (conf->type == DBG_TYPE_BREAKPOINT);
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cpuid = PCPU_GET(cpuid);
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if (!dbg_ready[cpuid]) {
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err = dbg_reset_state();
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if (err != 0)
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return (err);
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dbg_ready[cpuid] = TRUE;
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}
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addr = conf->address;
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if (is_bkpt) {
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@ -764,7 +751,7 @@ dbg_remove_xpoint(struct dbg_wb_conf *conf)
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d->dbg_wvr[i] = 0;
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d->dbg_wcr[i] = 0;
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/* Skip update command for the current CPU */
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if (cpu != cpuid)
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if (cpu != PCPU_GET(cpuid))
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pcpu->pc_dbreg_cmd = PC_DBREG_CMD_LOAD;
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}
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/* Ensure all data is written before waking other CPUs */
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@ -966,7 +953,7 @@ dbg_monitor_init(void)
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if (err == 0) {
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err = dbg_enable_monitor();
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if (err == 0) {
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dbg_capable = TRUE;
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atomic_set_int(&dbg_capable_var, 1);
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return;
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}
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}
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@ -977,19 +964,51 @@ dbg_monitor_init(void)
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CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg));
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void
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dbg_monitor_init_secondary(void)
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{
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u_int cpuid;
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int err;
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/*
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* This flag is set on the primary CPU
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* and its meaning is valid for other CPUs too.
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*/
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if (!dbg_capable())
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return;
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cpuid = PCPU_GET(cpuid);
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err = dbg_reset_state();
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if (err != 0) {
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/*
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* Something is very wrong.
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* WPs/BPs will not work correctly on this CPU.
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*/
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KASSERT(0, ("%s: Failed to reset Debug Architecture "
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"state on CPU%d", __func__, cpuid));
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/* Disable HW debug capabilities for all CPUs */
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atomic_set_int(&dbg_capable_var, 0);
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return;
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}
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err = dbg_enable_monitor();
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if (err != 0) {
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KASSERT(0, ("%s: Failed to enable Debug Monitor"
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" on CPU%d", __func__, cpuid));
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atomic_set_int(&dbg_capable_var, 0);
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}
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}
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void
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dbg_resume_dbreg(void)
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{
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struct dbreg *d;
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u_int cpuid;
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u_int i;
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int err;
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/*
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* This flag is set on the primary CPU
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* and its meaning is valid for other CPUs too.
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*/
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if (!dbg_capable)
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if (!dbg_capable())
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return;
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atomic_thread_fence_acq();
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@ -997,21 +1016,6 @@ dbg_resume_dbreg(void)
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switch (PCPU_GET(dbreg_cmd)) {
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case PC_DBREG_CMD_LOAD:
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d = (struct dbreg *)PCPU_PTR(dbreg);
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cpuid = PCPU_GET(cpuid);
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/* Reset Debug Architecture State if not done earlier */
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if (!dbg_ready[cpuid]) {
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err = dbg_reset_state();
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if (err != 0) {
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/*
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* Something is very wrong.
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* WPs/BPs will not work correctly in this CPU.
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*/
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panic("%s: Failed to reset Debug Architecture "
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"state on CPU%d", __func__, cpuid);
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}
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dbg_ready[cpuid] = TRUE;
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}
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/* Restore watchpoints */
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for (i = 0; i < dbg_watchpoint_num; i++) {
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@ -23,6 +23,9 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include "opt_smp.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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@ -60,8 +63,6 @@ __FBSDID("$FreeBSD$");
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#include <dev/fdt/fdt_common.h>
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#endif
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#include "opt_smp.h"
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extern struct pcpu __pcpu[];
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/* used to hold the AP's until we are ready to release them */
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struct mtx ap_boot_mtx;
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@ -176,6 +177,9 @@ init_secondary(int cpu)
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pcpu_init(pc, cpu, sizeof(struct pcpu));
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dpcpu_init(dpcpu[cpu - 1], cpu);
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#if __ARM_ARCH >= 6 && defined(DDB)
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dbg_monitor_init_secondary();
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#endif
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/* Signal our startup to BSP */
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atomic_add_rel_32(&mp_naps, 1);
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@ -45,6 +45,7 @@ enum dbg_access_t {
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#if __ARM_ARCH >= 6
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void dbg_monitor_init(void);
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void dbg_monitor_init_secondary(void);
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void dbg_show_watchpoint(void);
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int dbg_setup_watchpoint(db_expr_t, db_expr_t, enum dbg_access_t);
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int dbg_remove_watchpoint(db_expr_t, db_expr_t);
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@ -69,7 +70,10 @@ static __inline void
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dbg_monitor_init(void)
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{
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}
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static __inline void
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dbg_monitor_init_secondary(void)
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{
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}
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static __inline void
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dbg_resume_dbreg(void)
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{
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