Add support for cardbus card's chips. This will make the 3c575 cards
work once the rest of the cardbus infrastructure has been committed. Submitted by: Jonathan Chen <jon@spook.org>
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@ -57,6 +57,8 @@
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* 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
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* 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
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* 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
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* 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
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* 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
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* Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
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* Dell on-board 3c920 10/100Mbps/RJ-45
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* Dell Precision on-board 3c905B 10/100Mbps/RJ-45
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@ -191,6 +193,10 @@ static struct xl_type xl_devs[] = {
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"3Com 3c556 Fast Etherlink XL" },
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{ TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
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"3Com 3c556B Fast Etherlink XL" },
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{ TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
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"3Com 3c575B Fast Etherlink XL" },
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{ TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
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"3Com 3c575C Fast Etherlink XL" },
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{ 0, 0, NULL }
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};
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@ -287,6 +293,7 @@ static driver_t xl_driver = {
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static devclass_t xl_devclass;
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DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
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DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
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DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
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@ -699,6 +706,7 @@ static int xl_read_eeprom(sc, dest, off, cnt, swap)
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int err = 0, i;
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u_int16_t word = 0, *ptr;
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#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
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#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
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/* WARNING! DANGER!
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* It's easy to accidentally overwrite the rom content!
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* Note: the 3c575 uses 8bit EEPROM offsets.
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@ -713,7 +721,8 @@ static int xl_read_eeprom(sc, dest, off, cnt, swap)
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for (i = 0; i < cnt; i++) {
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if (sc->xl_flags & XL_FLAG_8BITROM)
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CSR_WRITE_2(sc, XL_W0_EE_CMD, (2<<8) | (off + i));
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CSR_WRITE_2(sc, XL_W0_EE_CMD,
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XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
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else
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CSR_WRITE_2(sc, XL_W0_EE_CMD,
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XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
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@ -1028,10 +1037,14 @@ static void xl_reset(sc)
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CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
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xl_wait(sc);
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if (sc->xl_flags & XL_FLAG_WEIRDRESET) {
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if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
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sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
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XL_SEL_WIN(2);
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CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
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XL_W2_RESET_OPTIONS) | 0x4010);
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XL_W2_RESET_OPTIONS)
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| ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
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| ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
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);
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}
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/* Wait a little while for the chip to get its brains in order. */
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@ -1159,6 +1172,8 @@ static void xl_choose_xcvr(sc, verbose)
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case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
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case TC_DEVICEID_HURRICANE_556: /* 3c556 */
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case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
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case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
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case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
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sc->xl_media = XL_MEDIAOPT_MII;
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sc->xl_xcvr = XL_XCVR_MII;
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if (verbose)
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@ -1220,10 +1235,20 @@ static int xl_attach(dev)
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if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
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pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
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sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
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XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET;
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XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
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XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
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if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
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sc->xl_flags |= XL_FLAG_8BITROM;
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if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
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pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
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sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
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XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
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if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
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sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
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if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
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sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
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/*
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* If this is a 3c905B, we have to check one extra thing.
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* The 905B supports power management and may be placed in
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@ -2037,7 +2062,7 @@ static void xl_intr(arg)
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XL_LOCK(sc);
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ifp = &sc->arpcom.ac_if;
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while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) {
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while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
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CSR_WRITE_2(sc, XL_COMMAND,
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XL_CMD_INTR_ACK|(status & XL_INTRS));
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@ -36,6 +36,7 @@
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#define XL_EE_WRITE 0x0040 /* write, 5 bit address */
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#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
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#define XL_EE_EWEN 0x0030 /* erase, no data needed */
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#define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
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#define XL_EE_BUSY 0x8000
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#define XL_EE_EADDR0 0x00 /* station address, first word */
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@ -248,6 +249,9 @@
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#define XL_RESETOPT_TEST100TX 0x1000
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#define XL_RESETOPT_TEST100RX 0x2000
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#define XL_RESETOPT_INVERT_LED 0x0010
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#define XL_RESETOPT_INVERT_MII 0x4000
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/*
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* Window 3 (fifo management)
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*/
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@ -553,6 +557,8 @@ struct xl_mii_frame {
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#define XL_FLAG_EEPROM_OFFSET_30 0x0004
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#define XL_FLAG_WEIRDRESET 0x0008
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#define XL_FLAG_8BITROM 0x0010
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#define XL_FLAG_INVERT_LED_PWR 0x0020
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#define XL_FLAG_INVERT_MII_PWR 0x0040
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struct xl_softc {
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struct arpcom arpcom; /* interface info */
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@ -657,6 +663,8 @@ struct xl_stats {
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#define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500
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#define TC_DEVICEID_HURRICANE_556 0x6055
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#define TC_DEVICEID_HURRICANE_556B 0x6056
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#define TC_DEVICEID_HURRICANE_575B 0x5157
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#define TC_DEVICEID_HURRICANE_575C 0x5257
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/*
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* PCI low memory base and low I/O base register, and
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