Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement. Sponsored by: ABT Systems Ltd
This commit is contained in:
Andrew Turner
parent
4ac1e8d30f
commit
037a0903ee
@ -243,49 +243,40 @@ struct cpu_functions sheeva_cpufuncs = {
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#ifdef CPU_MV_PJ4B
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struct cpu_functions pj4bv7_cpufuncs = {
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/* CPU functions */
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armv7_drain_writebuf, /* cpwait */
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.cf_cpwait = armv7_drain_writebuf,
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/* MMU functions */
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cpufunc_control, /* control */
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armv7_setttb, /* Setttb */
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.cf_control = cpufunc_control,
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.cf_setttb = armv7_setttb,
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/* TLB functions */
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armv7_tlb_flushID, /* tlb_flushID */
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armv7_tlb_flushID_SE, /* tlb_flushID_SE */
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armv7_tlb_flushID, /* tlb_flushD */
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armv7_tlb_flushID_SE, /* tlb_flushD_SE */
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.cf_tlb_flushID = armv7_tlb_flushID,
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.cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
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.cf_tlb_flushD = armv7_tlb_flushID,
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.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
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/* Cache operations */
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armv7_icache_sync_range, /* icache_sync_range */
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armv7_dcache_wbinv_all, /* dcache_wbinv_all */
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armv7_dcache_wbinv_range, /* dcache_wbinv_range */
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armv7_dcache_inv_range, /* dcache_inv_range */
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armv7_dcache_wb_range, /* dcache_wb_range */
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armv7_idcache_inv_all, /* idcache_inv_all */
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armv7_idcache_wbinv_all, /* idcache_wbinv_all */
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armv7_idcache_wbinv_range, /* idcache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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.cf_icache_sync_range = armv7_icache_sync_range,
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.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
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.cf_dcache_inv_range = armv7_dcache_inv_range,
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.cf_dcache_wb_range = armv7_dcache_wb_range,
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.cf_idcache_inv_all = armv7_idcache_inv_all,
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.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
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.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
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.cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
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.cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
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.cf_l2cache_inv_range = (void *)cpufunc_nullop,
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.cf_l2cache_wb_range = (void *)cpufunc_nullop,
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.cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
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/* Other functions */
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armv7_drain_writebuf, /* drain_writebuf */
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(void *)cpufunc_nullop, /* sleep */
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.cf_drain_writebuf = armv7_drain_writebuf,
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.cf_sleep = (void *)cpufunc_nullop,
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/* Soft functions */
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armv7_context_switch, /* context_switch */
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pj4bv7_setup /* cpu setup */
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.cf_context_switch = armv7_context_switch,
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.cf_setup = pj4bv7_setup
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};
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#endif /* CPU_MV_PJ4B */
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@ -446,64 +437,51 @@ struct cpu_functions fa526_cpufuncs = {
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#if defined(CPU_ARM1176)
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struct cpu_functions arm1176_cpufuncs = {
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/* CPU functions */
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cpufunc_nullop, /* cpwait */
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.cf_cpwait = cpufunc_nullop,
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/* MMU functions */
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cpufunc_control, /* control */
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arm11x6_setttb, /* Setttb */
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.cf_control = cpufunc_control,
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.cf_setttb = arm11x6_setttb,
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/* TLB functions */
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arm11_tlb_flushID, /* tlb_flushID */
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arm11_tlb_flushID_SE, /* tlb_flushID_SE */
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arm11_tlb_flushD, /* tlb_flushD */
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arm11_tlb_flushD_SE, /* tlb_flushD_SE */
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.cf_tlb_flushID = arm11_tlb_flushID,
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.cf_tlb_flushID_SE = arm11_tlb_flushID_SE,
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.cf_tlb_flushD = arm11_tlb_flushD,
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.cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
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/* Cache operations */
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arm11x6_icache_sync_range, /* icache_sync_range */
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arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
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armv6_dcache_wbinv_range, /* dcache_wbinv_range */
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armv6_dcache_inv_range, /* dcache_inv_range */
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armv6_dcache_wb_range, /* dcache_wb_range */
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armv6_idcache_inv_all, /* idcache_inv_all */
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arm11x6_idcache_wbinv_all, /* idcache_wbinv_all */
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arm11x6_idcache_wbinv_range, /* idcache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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.cf_icache_sync_range = arm11x6_icache_sync_range,
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.cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
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.cf_dcache_inv_range = armv6_dcache_inv_range,
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.cf_dcache_wb_range = armv6_dcache_wb_range,
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.cf_idcache_inv_all = armv6_idcache_inv_all,
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.cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all,
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.cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range,
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.cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
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.cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
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.cf_l2cache_inv_range = (void *)cpufunc_nullop,
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.cf_l2cache_wb_range = (void *)cpufunc_nullop,
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.cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
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/* Other functions */
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arm11_drain_writebuf, /* drain_writebuf */
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arm11x6_sleep, /* sleep */
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.cf_drain_writebuf = arm11_drain_writebuf,
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.cf_sleep = arm11x6_sleep,
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/* Soft functions */
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arm11_context_switch, /* context_switch */
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arm11x6_setup /* cpu setup */
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.cf_context_switch = arm11_context_switch,
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.cf_setup = arm11x6_setup
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};
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#endif /*CPU_ARM1176 */
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#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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struct cpu_functions cortexa_cpufuncs = {
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/* CPU functions */
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cpufunc_nullop, /* cpwait */
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.cf_cpwait = cpufunc_nullop,
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/* MMU functions */
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cpufunc_control, /* control */
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armv7_setttb, /* Setttb */
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.cf_control = cpufunc_control,
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.cf_setttb = armv7_setttb,
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/*
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* TLB functions. ARMv7 does all TLB ops based on a unified TLB model
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@ -511,45 +489,38 @@ struct cpu_functions cortexa_cpufuncs = {
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* same 'ID' functions for all 3 variations.
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*/
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armv7_tlb_flushID, /* tlb_flushID */
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armv7_tlb_flushID_SE, /* tlb_flushID_SE */
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armv7_tlb_flushID, /* tlb_flushD */
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armv7_tlb_flushID_SE, /* tlb_flushD_SE */
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.cf_tlb_flushID = armv7_tlb_flushID,
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.cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
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.cf_tlb_flushD = armv7_tlb_flushID,
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.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
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/* Cache operations */
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armv7_icache_sync_range, /* icache_sync_range */
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armv7_dcache_wbinv_all, /* dcache_wbinv_all */
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armv7_dcache_wbinv_range, /* dcache_wbinv_range */
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armv7_dcache_inv_range, /* dcache_inv_range */
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armv7_dcache_wb_range, /* dcache_wb_range */
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armv7_idcache_inv_all, /* idcache_inv_all */
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armv7_idcache_wbinv_all, /* idcache_wbinv_all */
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armv7_idcache_wbinv_range, /* idcache_wbinv_range */
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.cf_icache_sync_range = armv7_icache_sync_range,
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.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
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.cf_dcache_inv_range = armv7_dcache_inv_range,
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.cf_dcache_wb_range = armv7_dcache_wb_range,
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.cf_idcache_inv_all = armv7_idcache_inv_all,
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.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
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.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
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/*
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* Note: For CPUs using the PL310 the L2 ops are filled in when the
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* L2 cache controller is actually enabled.
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*/
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cpufunc_nullop, /* l2cache_wbinv_all */
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(void *)cpufunc_nullop, /* l2cache_wbinv_range */
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(void *)cpufunc_nullop, /* l2cache_inv_range */
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(void *)cpufunc_nullop, /* l2cache_wb_range */
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(void *)cpufunc_nullop, /* l2cache_drain_writebuf */
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.cf_l2cache_wbinv_all = cpufunc_nullop,
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.cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
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.cf_l2cache_inv_range = (void *)cpufunc_nullop,
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.cf_l2cache_wb_range = (void *)cpufunc_nullop,
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.cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
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/* Other functions */
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armv7_drain_writebuf, /* drain_writebuf */
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armv7_cpu_sleep, /* sleep */
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.cf_drain_writebuf = armv7_drain_writebuf,
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.cf_sleep = armv7_cpu_sleep,
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/* Soft functions */
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armv7_context_switch, /* context_switch */
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cortexa_setup /* cpu setup */
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.cf_context_switch = armv7_context_switch,
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.cf_setup = cortexa_setup
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};
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#endif /* CPU_CORTEXA */
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