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Provide armv4/v5 implementations of several of the armv6 cache maintenance

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functions.  This will make it possible to use the same busdma code for all
arm platforms v4 thru v7.
This commit is contained in:
ian 2015-10-24 21:25:53 +00:00
parent 138673038b
commit 03b5706014
1 changed files with 48 additions and 0 deletions
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48
sys/arm/include/cpu-v6.h
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@ -34,6 +34,7 @@
#error Only include this file in the kernel
#else
#include <machine/acle-compat.h>
#include "machine/atomic.h"
#include "machine/cpufunc.h"
#include "machine/cpuinfo.h"
@ -263,6 +264,12 @@ _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
#undef _WF0
#undef _WF1
#if __ARM_ARCH >= 6
/*
* Cache and TLB maintenance operations for armv6+ code. The #else block
* provides armv4/v5 implementations for a few of these used in common code.
*/
/*
* TLB maintenance operations.
*/
@ -558,6 +565,47 @@ cp15_ttbr_set(uint32_t reg)
tlb_flush_all_ng_local();
}
#else /* ! __ARM_ARCH >= 6 */
/*
* armv4/5 compatibility shims.
*
* These functions provide armv4 cache maintenance using the new armv6 names.
* Included here are just the functions actually used now in common code; it may
* be necessary to add things here over time.
*
* The callers of the dcache functions expect these routines to handle address
* and size values which are not aligned to cacheline boundaries; the armv4 and
* armv5 asm code handles that.
*/
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
cpu_l2cache_inv_range(va, size);
}
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
cpu_l2cache_inv_range(va, size);
cpu_dcache_inv_range(va, size);
}
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_wb_range(va, size);
cpu_l2cache_wb_range(va, size);
}
#endif /* __ARM_ARCH >= 6 */
#endif /* _KERNEL */
#endif /* !MACHINE_CPU_V6_H */