From 03ca7ae8a94b40e251a0cb628d999d87426a5501 Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Sun, 23 Mar 2008 05:31:35 +0000 Subject: [PATCH] For MSI capable hardwares, enable MSI enable bit in RL_CFG2 register. If MSI was disabled by hw.re.msi_disable tunable expliclty clear the MSI enable bit. --- sys/dev/re/if_re.c | 13 +++++++++++++ sys/pci/if_rlreg.h | 1 + 2 files changed, 14 insertions(+) diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index 538a5657afb5..143376c3f28a 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -1146,6 +1146,7 @@ re_attach(dev) u_int16_t re_did = 0; int error = 0, rid, i; int msic, reg; + uint8_t cfg; sc = device_get_softc(dev); sc->rl_dev = dev; @@ -1189,6 +1190,18 @@ re_attach(dev) } } + /* For MSI capable hardwares, explicitily set/clear MSI enable bit. */ + if (msic != 0) { + CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); + cfg = CSR_READ_1(sc, RL_CFG2); + if (sc->rl_msi != 0) + cfg |= RL_CFG2_MSI; + else + cfg &= ~RL_CFG2_MSI; + CSR_WRITE_1(sc, RL_CFG2, cfg); + CSR_WRITE_1(sc, RL_EECMD, 0); + } + /* Allocate interrupt */ if (sc->rl_msi == 0) { rid = 0; diff --git a/sys/pci/if_rlreg.h b/sys/pci/if_rlreg.h index d110df00643f..7e866891d14a 100644 --- a/sys/pci/if_rlreg.h +++ b/sys/pci/if_rlreg.h @@ -382,6 +382,7 @@ #define RL_CFG2_PCI66MHZ 0x01 #define RL_CFG2_PCI64BIT 0x08 #define RL_CFG2_AUXPWR 0x10 +#define RL_CFG2_MSI 0x20 /* * Config 3 register