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Do not setup machine exception vector.

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Sounds strange, but both RocketCore and lowRISC do not operate
if we set it.

All the known implementations (Spike, QEMU, RocketCore, lowRISC) uses
default machine trap vector address and operates fine with this.

Original Berkeley Boot Loader (bbl) does not set this as well.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
This commit is contained in:
br 2016-04-25 13:30:37 +00:00
parent 63312613f4
commit 03e30c2263
1 changed files with 0 additions and 7 deletions
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7
sys/riscv/riscv/locore.S
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@ -133,9 +133,6 @@ _start:
la t0, hardstack_end
csrw mscratch, t0
la t0, mentry
csrw mtvec, t0
li t0, 0
csrw sscratch, t0
@ -335,10 +332,6 @@ ENTRY(mpentry)
lw t1, 0(t0)
beqz t1, 1b
/* Setup machine exception vector */
la t0, mentry
csrw mtvec, t0
/* Build event queue ring for this core */
build_ring