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Updates to i.MX53:

Browse Source 
* Define support for the SDHCI driver, although it doesn't work yet
* Fix the memory mappings for IPU [1]

Reviewed by:	ray [1]
This commit is contained in:
rpaulo 2014-04-08 04:05:04 +00:00
parent 3a9d485daa
commit 04202d989d
8 changed files with 135 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
sys/arm/conf/DIGI-CCWMX53
View File

@ -169,6 +169,12 @@ device wlan_ccmp # 802.11 CCMP support
device wlan_tkip # 802.11 TKIP support
device wlan_amrr # AMRR transmit rate control algorithm
# MMC
#device sdhci # SD controller
#device mmc # SD/MMC protocol
#device mmcsd # SDCard disk device
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC
@ -177,6 +183,7 @@ makeoptions FDT_DTS_FILE=digi-ccwmx53.dts
# NOTE: serial console will be disabled if syscons enabled
# Uncomment following lines for framebuffer/syscons support
#device sc
#device vt
#device kbdmux
#options SC_DFLT_FONT # compile font in
#makeoptions SC_DFLT_FONT=cp437

3
sys/arm/freescale/imx/files.imx53
View File

@ -36,6 +36,9 @@ arm/freescale/imx/imx51_ccm.c standard
# i.MX5xx PATA controller
dev/ata/chipsets/ata-fsl.c optional imxata
# SDHCI/MMC
arm/freescale/imx/imx_sdhci.c optional sdhci
# USB OH3 controller (1 OTG, 3 EHCI)
arm/freescale/imx/imx_nop_usbphy.c optional ehci
dev/usb/controller/ehci_imx.c optional ehci

45
sys/arm/freescale/imx/imx51_ipuv3.c
View File

@ -260,7 +260,7 @@ ipu3_fb_probe(device_t dev)
if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
return (ENXIO);
device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
error = sc_probe_unit(device_get_unit(dev),
device_get_flags(dev) | SC_AUTODETECT_KBD);
@ -277,15 +277,19 @@ ipu3_fb_attach(device_t dev)
struct ipu3sc_softc *sc = device_get_softc(dev);
bus_space_tag_t iot;
bus_space_handle_t ioh;
phandle_t node;
pcell_t reg;
int err;
uintptr_t base;
if (ipu3sc_softc)
return (ENXIO);
ipu3sc_softc = sc;
device_printf(dev, "\tclock gate status is %d\n",
imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
if (bootverbose)
device_printf(dev, "clock gate status is %d\n",
imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
sc->dev = dev;
@ -300,58 +304,71 @@ ipu3_fb_attach(device_t dev)
sc = device_get_softc(dev);
sc->iot = iot = fdtbus_bs_tag;
device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
/*
* Retrieve the device address based on the start address in the
* DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
* address, so we just subtract IPU_CM_BASE to get the offset at which
* the IPU device was memory mapped.
* On i.MX53, the offset is 0.
*/
node = ofw_bus_get_node(dev);
if ((OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0)
base = 0;
else
base = fdt32_to_cpu(reg) - IPU_CM_BASE(0);
/* map controller registers */
err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
if (err)
goto fail_retarn_cm;
sc->cm_ioh = ioh;
/* map Display Multi FIFO Controller registers */
err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dmfc;
sc->dmfc_ioh = ioh;
/* map Display Interface 0 registers */
err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di0;
sc->di0_ioh = ioh;
/* map Display Interface 1 registers */
err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di1;
sc->di1_ioh = ioh;
/* map Display Processor registers */
err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dp;
sc->dp_ioh = ioh;
/* map Display Controller registers */
err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dc;
sc->dc_ioh = ioh;
/* map Image DMA Controller registers */
err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_idmac;
sc->idmac_ioh = ioh;
/* map CPMEM registers */
err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_cpmem;
sc->cpmem_ioh = ioh;
/* map DCTEMPL registers */
err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_dctmpl;
sc->dctmpl_ioh = ioh;

47
sys/arm/freescale/imx/imx51_ipuv3_fbd.c
View File

@ -190,7 +190,7 @@ ipu3_fb_probe(device_t dev)
if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
return (ENXIO);
device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
return (BUS_PROBE_DEFAULT);
}
@ -201,70 +201,87 @@ ipu3_fb_attach(device_t dev)
struct ipu3sc_softc *sc = device_get_softc(dev);
bus_space_tag_t iot;
bus_space_handle_t ioh;
int err;
phandle_t node;
pcell_t reg;
int err;
uintptr_t base;
ipu3sc_softc = sc;
device_printf(dev, "\tclock gate status is %d\n",
imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
if (bootverbose)
device_printf(dev, "clock gate status is %d\n",
imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
sc->dev = dev;
sc = device_get_softc(dev);
sc->iot = iot = fdtbus_bs_tag;
device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
/*
* Retrieve the device address based on the start address in the
* DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
* address, so we just subtract IPU_CM_BASE to get the offset at which
* the IPU device was memory mapped.
* On i.MX53, the offset is 0.
*/
node = ofw_bus_get_node(dev);
if ((OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0)
base = 0;
else
base = fdt32_to_cpu(reg) - IPU_CM_BASE(0);
/* map controller registers */
err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
if (err)
goto fail_retarn_cm;
sc->cm_ioh = ioh;
/* map Display Multi FIFO Controller registers */
err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dmfc;
sc->dmfc_ioh = ioh;
/* map Display Interface 0 registers */
err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di0;
sc->di0_ioh = ioh;
/* map Display Interface 1 registers */
err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di1;
sc->di1_ioh = ioh;
/* map Display Processor registers */
err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dp;
sc->dp_ioh = ioh;
/* map Display Controller registers */
err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dc;
sc->dc_ioh = ioh;
/* map Image DMA Controller registers */
err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_idmac;
sc->idmac_ioh = ioh;
/* map CPMEM registers */
err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_cpmem;
sc->cpmem_ioh = ioh;
/* map DCTEMPL registers */
err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
&ioh);
if (err)
goto fail_retarn_dctmpl;
sc->dctmpl_ioh = ioh;

79
sys/arm/freescale/imx/imx51_ipuv3reg.h
View File

@ -877,43 +877,46 @@
#define GPU_BASE 0x30000000
#define GPU_SIZE 0x10000000
/* Image Prossasing Unit */
#define IPU_BASE 0x40000000
#define IPU_CM_BASE (IPU_BASE + 0x1e000000)
#define IPU_CM_SIZE 0x8000
#define IPU_IDMAC_BASE (IPU_BASE + 0x1e008000)
#define IPU_IDMAC_SIZE 0x8000
#define IPU_DP_BASE (IPU_BASE + 0x1e018000)
#define IPU_DP_SIZE 0x8000
#define IPU_IC_BASE (IPU_BASE + 0x1e020000)
#define IPU_IC_SIZE 0x8000
#define IPU_IRT_BASE (IPU_BASE + 0x1e028000)
#define IPU_IRT_SIZE 0x8000
#define IPU_CSI0_BASE (IPU_BASE + 0x1e030000)
#define IPU_CSI0_SIZE 0x8000
#define IPU_CSI1_BASE (IPU_BASE + 0x1e038000)
#define IPU_CSI1_SIZE 0x8000
#define IPU_DI0_BASE (IPU_BASE + 0x1e040000)
#define IPU_DI0_SIZE 0x8000
#define IPU_DI1_BASE (IPU_BASE + 0x1e048000)
#define IPU_DI1_SIZE 0x8000
#define IPU_SMFC_BASE (IPU_BASE + 0x1e050000)
#define IPU_SMFC_SIZE 0x8000
#define IPU_DC_BASE (IPU_BASE + 0x1e058000)
#define IPU_DC_SIZE 0x8000
#define IPU_DMFC_BASE (IPU_BASE + 0x1e060000)
#define IPU_DMFC_SIZE 0x8000
#define IPU_VDI_BASE (IPU_BASE + 0x1e068000)
#define IPU_VDI_SIZE 0x8000
#define IPU_CPMEM_BASE (IPU_BASE + 0x1f000000)
#define IPU_CPMEM_SIZE 0x20000
#define IPU_LUT_BASE (IPU_BASE + 0x1f020000)
#define IPU_LUT_SIZE 0x20000
#define IPU_SRM_BASE (IPU_BASE + 0x1f040000)
#define IPU_SRM_SIZE 0x20000
#define IPU_TPM_BASE (IPU_BASE + 0x1f060000)
#define IPU_TPM_SIZE 0x20000
#define IPU_DCTMPL_BASE (IPU_BASE + 0x1f080000)
#define IPU_DCTMPL_SIZE 0x20000
/*
* Image Processing Unit
*
* All addresses are relative to the base SoC address.
*/
#define IPU_CM_BASE(_base) ((_base) + 0x1e000000)
#define IPU_CM_SIZE 0x8000
#define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000)
#define IPU_IDMAC_SIZE 0x8000
#define IPU_DP_BASE(_base) ((_base) + 0x1e018000)
#define IPU_DP_SIZE 0x8000
#define IPU_IC_BASE(_base) ((_base) + 0x1e020000)
#define IPU_IC_SIZE 0x8000
#define IPU_IRT_BASE(_base) ((_base) + 0x1e028000)
#define IPU_IRT_SIZE 0x8000
#define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000)
#define IPU_CSI0_SIZE 0x8000
#define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000)
#define IPU_CSI1_SIZE 0x8000
#define IPU_DI0_BASE(_base) ((_base) + 0x1e040000)
#define IPU_DI0_SIZE 0x8000
#define IPU_DI1_BASE(_base) ((_base) + 0x1e048000)
#define IPU_DI1_SIZE 0x8000
#define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000)
#define IPU_SMFC_SIZE 0x8000
#define IPU_DC_BASE(_base) ((_base) + 0x1e058000)
#define IPU_DC_SIZE 0x8000
#define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000)
#define IPU_DMFC_SIZE 0x8000
#define IPU_VDI_BASE(_base) ((_base) + 0x1e068000)
#define IPU_VDI_SIZE 0x8000
#define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000)
#define IPU_CPMEM_SIZE 0x20000
#define IPU_LUT_BASE(_base) ((_base) + 0x1f020000)
#define IPU_LUT_SIZE 0x20000
#define IPU_SRM_BASE(_base) ((_base) + 0x1f040000)
#define IPU_SRM_SIZE 0x20000
#define IPU_TPM_BASE(_base) ((_base) + 0x1f060000)
#define IPU_TPM_SIZE 0x20000
#define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000)
#define IPU_DCTMPL_SIZE 0x20000
#endif /* _ARM_IMX_IMX51_IPUV3REG_H */

2
sys/boot/fdt/dts/arm/digi-ccwmx53.dts
View File

@ -46,7 +46,7 @@
};
localbus@18000000 {
ipu3@18000000 {
ipu3@1E000000 {
status = "okay";
};
};

2
sys/boot/fdt/dts/arm/imx53-qsb.dts
View File

@ -47,7 +47,7 @@
};
localbus@18000000 {
ipu3@18000000 {
ipu3@1E000000 {
status = "okay";
};
};

38
sys/boot/fdt/dts/arm/imx53x.dtsi
View File

@ -657,27 +657,27 @@
ranges;
vga: ipu3@18000000 {
vga: ipu3@1E000000 {
compatible = "fsl,ipu3";
reg = <
0x18000000 0x08000 /* CM */
0x18008000 0x08000 /* IDMAC */
0x18018000 0x08000 /* DP */
0x18020000 0x08000 /* IC */
0x18028000 0x08000 /* IRT */
0x18030000 0x08000 /* CSI0 */
0x18038000 0x08000 /* CSI1 */
0x18040000 0x08000 /* DI0 */
0x18048000 0x08000 /* DI1 */
0x18050000 0x08000 /* SMFC */
0x18058000 0x08000 /* DC */
0x18060000 0x08000 /* DMFC */
0x18068000 0x08000 /* VDI */
0x19000000 0x20000 /* CPMEM */
0x19020000 0x20000 /* LUT */
0x19040000 0x20000 /* SRM */
0x19060000 0x20000 /* TPM */
0x19080000 0x20000 /* DCTMPL */
0x1E000000 0x08000 /* CM */
0x1E008000 0x08000 /* IDMAC */
0x1E018000 0x08000 /* DP */
0x1E020000 0x08000 /* IC */
0x1E028000 0x08000 /* IRT */
0x1E030000 0x08000 /* CSI0 */
0x1E038000 0x08000 /* CSI1 */
0x1E040000 0x08000 /* DI0 */
0x1E048000 0x08000 /* DI1 */
0x1E050000 0x08000 /* SMFC */
0x1E058000 0x08000 /* DC */
0x1E060000 0x08000 /* DMFC */
0x1E068000 0x08000 /* VDI */
0x1F000000 0x20000 /* CPMEM */
0x1F020000 0x20000 /* LUT */
0x1F040000 0x20000 /* SRM */
0x1F060000 0x20000 /* TPM */
0x1F080000 0x20000 /* DCTMPL */
>;
interrupt-parent = <&tzic>;
interrupts = <