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Use a TR of size 1 << IA64_ID_PAGE_SHIFT instead of 16M to avoid

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overlapping TR/TC entries (which results in a machine check). Note
that we don't look at the size of the memory descriptor, because
it doesn't guarantee non-overlap.

With this change, a UP kernel could boot on a Intel Tiger4 machine
with the following options:

options         LOG2_ID_PAGE_SIZE=26		# 64M
options         LOG2_PAGE_SIZE=14               # 16K

Approved by: marcel
This commit is contained in:
arun 2003-10-24 04:56:58 +00:00
parent b3207a61e7
commit 05b0056432
1 changed files with 1 additions and 2 deletions
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3
sys/ia64/ia64/machdep.c
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@ -418,8 +418,7 @@ map_port_space(void)
__asm __volatile("rsm psr.ic|psr.i");
__asm __volatile("srlz.d");
__asm __volatile("mov cr.ifa=%0" :: "r"(ia64_port_base));
/* XXX We should use the size from the memory descriptor. */
__asm __volatile("mov cr.itir=%0" :: "r"(24 << 2));
__asm __volatile("mov cr.itir=%0" :: "r"(IA64_ID_PAGE_SHIFT << 2));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(*(u_int64_t*)&pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
__asm __volatile("srlz.d");