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Rework the Global TX timeout handling to look more like ath9k.

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It correctly now sets the AR_IMR BCNMISC register, along with
the GTT register in AR_IMR_S2.
This commit is contained in:
adrian 2011-04-18 14:03:05 +00:00
parent 154daa04a7
commit 05db000c10
2 changed files with 12 additions and 3 deletions
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10
sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
View File

@ -234,14 +234,20 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
mask2 |= AR_IMR_S2_DTIMSYNC;
if (ints & HAL_INT_CABEND)
mask2 |= (AR_IMR_S2_CABEND );
if (ints & HAL_INT_GTT)
mask2 |= AR_IMR_S2_GTT;
if (ints & HAL_INT_CST)
mask2 |= AR_IMR_S2_CST;
if (ints & HAL_INT_TSFOOR)
mask2 |= AR_IMR_S2_TSFOOR;
}
if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
mask |= AR_IMR_BCNMISC;
if (ints & HAL_INT_GTT)
mask2 |= AR_IMR_S2_GTT;
if (ints & HAL_INT_CST)
mask2 |= AR_IMR_S2_CST;
}
/* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
OS_REG_WRITE(ah, AR_IMR, mask);

5
sys/dev/ath/if_ath.c
View File

@ -1563,7 +1563,10 @@ ath_init(void *arg)
/* Enable global TX timeout statistics if available */
if (ath_hal_gtxto_supported(ah))
sc->sc_imask |= (HAL_INT_GTT & HAL_INT_BMISC);
sc->sc_imask |= HAL_INT_GTT;
DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
__func__, sc->sc_imask);
ifp->if_drv_flags |= IFF_DRV_RUNNING;
callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);