Fixes a few style(9) issues, remove extra blank lines.
No functional changes. Sponsored by: Rubicon Comunications (Netgate)
This commit is contained in:
Luiz Otavio O Souza
parent
fb9cfe551b
commit
0620372f28
@ -148,8 +148,7 @@ static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS);
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* Packets with more segments than this will be defragmented before
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* they are queued.
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*/
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#define CPSW_TXFRAGS 8
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#define CPSW_TXFRAGS 8
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/*
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* TODO: The CPSW subsystem (CPSW_SS) can drive two independent PHYs
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@ -251,7 +250,7 @@ static struct cpsw_stat {
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* Basic debug support.
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*/
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#define IF_DEBUG(sc) if (sc->cpsw_if_flags & IFF_DEBUG)
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#define IF_DEBUG(sc) if (sc->cpsw_if_flags & IFF_DEBUG)
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static void
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cpsw_debugf_head(const char *funcname)
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@ -274,35 +273,34 @@ cpsw_debugf(const char *fmt, ...)
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}
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#define CPSW_DEBUGF(a) do { \
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IF_DEBUG(sc) { \
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cpsw_debugf_head(__func__); \
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cpsw_debugf a; \
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} \
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#define CPSW_DEBUGF(a) do { \
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IF_DEBUG(sc) { \
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cpsw_debugf_head(__func__); \
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cpsw_debugf a; \
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} \
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} while (0)
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/*
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* Locking macros
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*/
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#define CPSW_TX_LOCK(sc) do { \
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#define CPSW_TX_LOCK(sc) do { \
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mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->tx.lock); \
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} while (0)
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#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
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#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
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#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
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#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
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#define CPSW_RX_LOCK(sc) do { \
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#define CPSW_RX_LOCK(sc) do { \
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mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
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mtx_lock(&(sc)->rx.lock); \
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} while (0)
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#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock)
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#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED)
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#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock)
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#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED)
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#define CPSW_GLOBAL_LOCK(sc) do { \
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if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) != \
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#define CPSW_GLOBAL_LOCK(sc) do { \
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if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) != \
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(mtx_owned(&(sc)->rx.lock) ? 1 : 0)) { \
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panic("cpsw deadlock possibility detection!"); \
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} \
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@ -310,12 +308,12 @@ cpsw_debugf(const char *fmt, ...)
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mtx_lock(&(sc)->rx.lock); \
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} while (0)
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#define CPSW_GLOBAL_UNLOCK(sc) do { \
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CPSW_RX_UNLOCK(sc); \
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CPSW_TX_UNLOCK(sc); \
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#define CPSW_GLOBAL_UNLOCK(sc) do { \
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CPSW_RX_UNLOCK(sc); \
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CPSW_TX_UNLOCK(sc); \
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} while (0)
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#define CPSW_GLOBAL_LOCK_ASSERT(sc) do { \
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#define CPSW_GLOBAL_LOCK_ASSERT(sc) do { \
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CPSW_TX_LOCK_ASSERT(sc); \
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CPSW_RX_LOCK_ASSERT(sc); \
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} while (0)
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@ -328,7 +326,7 @@ cpsw_debugf(const char *fmt, ...)
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#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16))
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#define cpsw_cpdma_bd_paddr(sc, slot) \
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#define cpsw_cpdma_bd_paddr(sc, slot) \
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BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset)
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#define cpsw_cpdma_read_bd(sc, slot, val) \
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bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
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@ -336,16 +334,16 @@ cpsw_debugf(const char *fmt, ...)
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bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
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#define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \
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cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
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#define cpsw_cpdma_read_bd_flags(sc, slot) \
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#define cpsw_cpdma_read_bd_flags(sc, slot) \
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bus_read_2(sc->mem_res, slot->bd_offset + 14)
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#define cpsw_write_hdp_slot(sc, queue, slot) \
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cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
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#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
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#define cpsw_read_cp(sc, queue) \
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#define cpsw_read_cp(sc, queue) \
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cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
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#define cpsw_write_cp(sc, queue, val) \
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#define cpsw_write_cp(sc, queue, val) \
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cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
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#define cpsw_write_cp_slot(sc, queue, slot) \
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#define cpsw_write_cp_slot(sc, queue, slot) \
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cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
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#if 0
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@ -403,13 +401,12 @@ cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
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}
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}
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#define CPSW_DUMP_SLOT(cs, slot) do { \
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#define CPSW_DUMP_SLOT(cs, slot) do { \
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IF_DEBUG(sc) { \
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cpsw_dump_slot(sc, slot); \
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} \
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} while (0)
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static void
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cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
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{
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@ -429,13 +426,12 @@ cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
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printf("\n");
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}
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#define CPSW_DUMP_QUEUE(sc, q) do { \
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#define CPSW_DUMP_QUEUE(sc, q) do { \
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IF_DEBUG(sc) { \
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cpsw_dump_queue(sc, q); \
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} \
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} while (0)
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/*
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*
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* Device Probe, Attach, Detach.
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@ -456,7 +452,6 @@ cpsw_probe(device_t dev)
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return (BUS_PROBE_DEFAULT);
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}
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static void
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cpsw_init_slots(struct cpsw_softc *sc)
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{
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@ -1303,7 +1298,6 @@ cpsw_miibus_statchg(device_t dev)
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*
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*/
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static void
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cpsw_intr_rx(void *arg)
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{
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@ -2266,4 +2260,3 @@ cpsw_add_sysctls(struct cpsw_softc *sc)
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CTLFLAG_RD, NULL, "Watchdog Statistics");
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cpsw_add_watchdog_sysctls(ctx, node, sc);
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}
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@ -29,103 +29,103 @@
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#ifndef _IF_CPSWREG_H
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#define _IF_CPSWREG_H
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#define CPSW_SS_OFFSET 0x0000
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#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
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#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
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#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
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#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
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#define CPSW_SS_OFFSET 0x0000
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#define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
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#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
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#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
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#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
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#define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
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#define CPSW_PORT_OFFSET 0x0100
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#define CPSW_PORT_OFFSET 0x0100
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#define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
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#define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
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#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
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#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
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#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
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#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
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#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
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#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
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#define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C)
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#define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020)
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#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
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#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
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#define CPSW_CPDMA_OFFSET 0x0800
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#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
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#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
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#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
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#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
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#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
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#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
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#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
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#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
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#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
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#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
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#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
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#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
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#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
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#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
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#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
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#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
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#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
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#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
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#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
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#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
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#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
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#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
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#define CPSW_CPDMA_OFFSET 0x0800
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#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
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#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
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#define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14)
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#define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18)
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#define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c)
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#define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20)
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#define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24)
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#define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28)
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#define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80)
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#define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84)
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#define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88)
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#define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C)
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#define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94)
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#define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0)
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#define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4)
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#define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8)
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#define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc)
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#define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0)
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#define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4)
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#define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8)
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#define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC)
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#define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
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#define CPSW_STATS_OFFSET 0x0900
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#define CPSW_STATS_OFFSET 0x0900
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#define CPSW_STATERAM_OFFSET 0x0A00
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#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
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#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
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#define CPSW_STATERAM_OFFSET 0x0A00
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#define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
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#define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
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#define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
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#define CPSW_CPTS_OFFSET 0x0C00
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#define CPSW_CPTS_OFFSET 0x0C00
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#define CPSW_ALE_OFFSET 0x0D00
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#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
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#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
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#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
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#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
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#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
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#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
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#define CPSW_ALE_OFFSET 0x0D00
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#define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08)
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#define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20)
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#define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34)
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#define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38)
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#define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C)
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#define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
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/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
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#define CPSW_SL_OFFSET 0x0D80
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#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
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#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
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#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
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#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
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#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
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#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
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#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
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#define CPSW_SL_OFFSET 0x0D80
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#define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
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#define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
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#define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
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#define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
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#define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
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#define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
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#define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
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#define MDIO_OFFSET 0x1000
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#define MDIOCONTROL (MDIO_OFFSET + 0x04)
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#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
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#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
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#define MDIO_OFFSET 0x1000
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#define MDIOCONTROL (MDIO_OFFSET + 0x04)
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#define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80)
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#define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84)
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||||
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||||
#define CPSW_WR_OFFSET 0x1200
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#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
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||||
#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
|
||||
#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
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#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
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||||
#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
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||||
#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
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||||
#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
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#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
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||||
#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
|
||||
#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
|
||||
#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
|
||||
#define CPSW_WR_OFFSET 0x1200
|
||||
#define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04)
|
||||
#define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08)
|
||||
#define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c)
|
||||
#define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
|
||||
#define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
|
||||
#define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
|
||||
#define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
|
||||
#define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
|
||||
#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
|
||||
#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
|
||||
#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
|
||||
|
||||
#define CPSW_CPPI_RAM_OFFSET 0x2000
|
||||
#define CPSW_CPPI_RAM_OFFSET 0x2000
|
||||
#define CPSW_CPPI_RAM_SIZE 0x2000
|
||||
|
||||
#define CPSW_MEMWINDOW_SIZE 0x4000
|
||||
|
||||
#define CPDMA_BD_SOP (1<<15)
|
||||
#define CPDMA_BD_EOP (1<<14)
|
||||
#define CPDMA_BD_OWNER (1<<13)
|
||||
#define CPDMA_BD_EOQ (1<<12)
|
||||
#define CPDMA_BD_TDOWNCMPLT (1<<11)
|
||||
#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
|
||||
#define CPDMA_BD_SOP (1<<15)
|
||||
#define CPDMA_BD_EOP (1<<14)
|
||||
#define CPDMA_BD_OWNER (1<<13)
|
||||
#define CPDMA_BD_EOQ (1<<12)
|
||||
#define CPDMA_BD_TDOWNCMPLT (1<<11)
|
||||
#define CPDMA_BD_PKT_ERR_MASK (3<< 4)
|
||||
|
||||
struct cpsw_cpdma_bd {
|
||||
volatile uint32_t next;
|
||||
|
||||
@ -29,15 +29,15 @@
|
||||
#ifndef _IF_CPSWVAR_H
|
||||
#define _IF_CPSWVAR_H
|
||||
|
||||
#define CPSW_INTR_COUNT 4
|
||||
#define CPSW_INTR_COUNT 4
|
||||
|
||||
/* MII BUS */
|
||||
#define CPSW_MIIBUS_RETRIES 5
|
||||
#define CPSW_MIIBUS_DELAY 1000
|
||||
#define CPSW_MIIBUS_RETRIES 5
|
||||
#define CPSW_MIIBUS_DELAY 1000
|
||||
|
||||
#define CPSW_MAX_ALE_ENTRIES 1024
|
||||
#define CPSW_MAX_ALE_ENTRIES 1024
|
||||
|
||||
#define CPSW_SYSCTL_COUNT 34
|
||||
#define CPSW_SYSCTL_COUNT 34
|
||||
|
||||
struct cpsw_slot {
|
||||
uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user