Fix PPC64 kernel build with clang8 + lld8
This patch fixes the following lld link errors: - unsupported dynamic relocations on read-only sections - out-of-range TOC references Submitted by: git_bdragon.rtk0.net Reviewed by: jhibbits, luporl MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D19352
This commit is contained in:
Leandro Lupori
parent
0a3b1d8090
commit
0632bb89db
@ -98,7 +98,8 @@ SECTIONS
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.opd : ALIGN(8) { KEEP (*(.opd)) }
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.branch_lt : ALIGN(8) { *(.branch_lt) }
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. = ALIGN(4096);
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.got : ALIGN(8) { __tocbase = .; *(.got .toc) }
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.got : ALIGN(8) { __tocbase = .; *(.got) }
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.toc : ALIGN(8) { *(.toc) }
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.dynamic : { *(.dynamic) } :text :dynamic
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/* Put .ctors and .dtors next to the .got2 section, so that the pointers
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@ -317,29 +317,33 @@ CNAME(rstcode):
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* processor is waking up from power saving mode
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* It is software reset when 46:47 = 0b00
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*/
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/* 0x00 */
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ld %r2,TRAP_GENTRAP(0) /* Real-mode &generictrap */
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mfsrr1 %r9 /* Load SRR1 into r9 */
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andis. %r9,%r9,0x3 /* Logic AND with 46:47 bits */
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beq 2f /* Branch if software reset */
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bl 1f
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.llong cpu_wakeup_handler
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/* It is software reset */
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/* 0x10 */
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/* Reset was wakeup */
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addi %r9,%r2,(cpu_wakeup_handler-generictrap)
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b 1f /* Was power save, do the wakeup */
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/* Reset was software reset */
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/* Explicitly set MSR[SF] */
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2: mfmsr %r9
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li %r8,1
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/* 0x20 */
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insrdi %r9,%r8,1,0
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mtmsrd %r9
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isync
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bl 1f
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.llong cpu_reset_handler /* Make sure to maintain 8-byte alignment */
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addi %r9,%r2,(cpu_reset_handler-generictrap)
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1: mflr %r9
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ld %r9,0(%r9)
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mtlr %r9
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blr
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/* 0x30 */
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1: mtlr %r9
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blr /* Branch to either cpu_reset_handler
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* or cpu_wakeup_handler.
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*/
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CNAME(rstcodeend):
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cpu_reset_handler:
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@ -459,52 +463,59 @@ CNAME(hypertrapcode):
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addi %r1,%r1,(generichypertrap-generictrap)
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mtlr %r1
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li %r1, 0xe0 /* How to get the vector from LR */
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blrl /* Branch to generictrap */
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blrl /* Branch to generichypertrap */
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CNAME(hypertrapcodeend):
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/*
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* For SLB misses: do special things for the kernel
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*
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* Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
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* Note: SPRG1 is always safe to overwrite any time the MMU was on, which is
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* the only time this can be called.
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*/
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.globl CNAME(slbtrap),CNAME(slbtrapend)
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.p2align 3
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CNAME(slbtrap):
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/* 0x00 */
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mtsprg1 %r1 /* save SP */
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GET_CPUINFO(%r1)
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std %r2,(PC_SLBSAVE+16)(%r1)
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mfcr %r2 /* save CR */
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std %r2,(PC_SLBSAVE+104)(%r1)
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std %r2,(PC_SLBSAVE+16)(%r1) /* save r2 */
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mfcr %r2
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/* 0x10 */
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std %r2,(PC_SLBSAVE+104)(%r1) /* save CR */
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mfsrr1 %r2 /* test kernel mode */
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mtcr %r2
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bf 17,2f /* branch if PSL_PR is false */
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/* 0x20 */
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/* User mode */
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ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
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mtcr %r2
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ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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/* 52 bytes so far */
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bl 1f
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.llong generictrap
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1: mflr %r1
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ld %r1,0(%r1)
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ld %r2,(PC_SLBSAVE+104)(%r1)
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mtcr %r2 /* restore CR */
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ld %r2,(PC_SLBSAVE+16)(%r1) /* restore r2 */
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mflr %r1
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/* 0x30 */
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mtsprg2 %r1 /* save LR in SPRG2 */
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ld %r1,TRAP_GENTRAP(0) /* real-mode &generictrap */
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mtlr %r1
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li %r1, 0x80 /* How to get the vector from LR */
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/* 0x40 */
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blrl /* Branch to generictrap */
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/* 84 bytes */
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2: mflr %r2 /* Save the old LR in r2 */
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nop
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bl 3f /* Begin dance to jump to kern_slbtrap*/
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.llong kern_slbtrap
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3: mflr %r1
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ld %r1,0(%r1)
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/* Kernel mode */
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ld %r1,TRAP_GENTRAP(0) /* Real-mode &generictrap */
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addi %r1,%r1,(kern_slbtrap-generictrap)
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/* 0x50 */
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mtlr %r1
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GET_CPUINFO(%r1)
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blrl /* 124 bytes -- 4 to spare */
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blrl /* Branch to kern_slbtrap */
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/* must fit in 128 bytes! */
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CNAME(slbtrapend):
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/*
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* On entry:
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* SPRG1: SP
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* r1: pcpu
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* r2: LR
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* LR: branch address in trap region
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*/
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kern_slbtrap:
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std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
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std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
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@ -512,7 +523,7 @@ kern_slbtrap:
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/* Check if this needs to be handled as a regular trap (userseg miss) */
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mflr %r2
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andi. %r2,%r2,0xff80
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cmpwi %r2,0x380
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cmpwi %r2,EXC_DSE
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bne 1f
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mfdar %r2
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b 2f
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@ -641,14 +652,8 @@ CNAME(alitrap):
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mflr %r28 /* save LR */
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mfcr %r29 /* save CR */
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/* Begin dance to branch to s_trap in a bit */
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b 1f
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.p2align 3
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1: nop
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bl 1f
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.llong s_trap
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1: mflr %r31
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ld %r31,0(%r31)
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ld %r31,TRAP_GENTRAP(0)
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addi %r31,%r31,(s_trap - generictrap)
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mtlr %r31
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/* Put our exception vector in SPRG3 */
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@ -658,7 +663,7 @@ CNAME(alitrap):
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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blrl
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blrl /* Branch to s_trap */
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CNAME(aliend):
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/*
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@ -681,12 +686,10 @@ CNAME(dsitrap):
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mfsrr1 %r31 /* test kernel mode */
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mtcr %r31
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mflr %r28 /* save LR (SP already saved) */
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bl 1f /* Begin branching to disitrap */
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.llong disitrap
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1: mflr %r1
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ld %r1,0(%r1)
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ld %r1,TRAP_GENTRAP(0)
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addi %r1,%r1,(disitrap-generictrap)
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mtlr %r1
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blrl /* Branch to generictrap */
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blrl /* Branch to disitrap */
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CNAME(dsiend):
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/*
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@ -956,7 +959,7 @@ CNAME(dblow):
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mtlr %r1
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li %r1, 0 /* How to get the vector from LR */
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blrl /* Branch to generictrap */
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/* No fallthrough */
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1:
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GET_CPUINFO(%r1)
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std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
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@ -966,12 +969,9 @@ CNAME(dblow):
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std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
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std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
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mflr %r28 /* save LR */
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nop /* alignment */
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bl 9f /* Begin branch */
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.llong dbtrap
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9: mflr %r1
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ld %r1,0(%r1)
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ld %r1,TRAP_GENTRAP(0)
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addi %r1,%r1,(dbtrap-generictrap)
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mtlr %r1
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blrl /* Branch to generictrap */
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blrl /* Branch to dbtrap */
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CNAME(dbend):
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#endif /* KDB */
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@ -31,7 +31,6 @@
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#include <machine/asm.h>
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.globl CNAME(power_save_sequence)
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.p2align 3
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ENTRY(enter_idle_powerx)
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mfsprg0 %r3 /* Get the pcpu pointer */
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@ -65,11 +64,9 @@ ENTRY(enter_idle_powerx)
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std %r1,PCB_SP(%r3) /* Save the stack pointer */
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std %r2,PCB_TOC(%r3) /* Save the TOC pointer */
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/* Set where we want to jump */
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bl 1f
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.llong power_save_sequence /* Remember about 8 byte alignment */
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1: mflr %r3
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ld %r3,0(%r3)
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addi %r3,%r3,power_save_sequence-1b
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mtsrr0 %r3
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/* Set MSR */
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@ -82,7 +79,7 @@ ENTRY(enter_idle_powerx)
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rfid
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.p2align 2
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CNAME(power_save_sequence):
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power_save_sequence:
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bl 1f
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.llong 0x0 /* Playground for power-save sequence */
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1: mflr %r3
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