Enable ArmadaXP using INTRNG interrupt controller
Defining INTRNG remove some necessary registers and declarations of pic_init_secondary, pic_ipi_send, pic_ipi_read and pic_ipi_clear. Because Marvell ArmadaXP and Armada38X always use INTRNG, include all INTRNG code and remove code that does not use it. Separate pic registers declarations for Armada38X are unnecessary, it works properly with ArmadaXP config. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: andrew Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14734
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@ -88,3 +88,5 @@ device pci
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options FDT # Configure using FDT/DTB data
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options FDT_DTB_STATIC
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makeoptions FDT_DTS_FILE=db78460.dts
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options INTRNG
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@ -84,13 +84,6 @@ int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *);
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#define NIRQ 288
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#elif defined(CPU_ARM1176)
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#define NIRQ 128
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#elif defined(SOC_MV_ARMADAXP)
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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#define ERR_IRQ (MAIN_IRQ_NUM)
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#define MSI_IRQ_NUM 32
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#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
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#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
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#else
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#define NIRQ 32
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#endif
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@ -103,12 +103,10 @@ __FBSDID("$FreeBSD$");
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#define MPIC_PPI 32
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#ifdef INTRNG
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struct mv_mpic_irqsrc {
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struct intr_irqsrc mmi_isrc;
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u_int mmi_irq;
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};
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#endif
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struct mv_mpic_softc {
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device_t sc_dev;
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@ -120,9 +118,7 @@ struct mv_mpic_softc {
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bus_space_tag_t drbl_bst;
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bus_space_handle_t drbl_bsh;
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struct mtx mtx;
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#ifdef INTRNG
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struct mv_mpic_irqsrc * mpic_isrcs;
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#endif
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int nirqs;
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void * intr_hand;
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};
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@ -155,10 +151,12 @@ static void mpic_mask_irq(uintptr_t nb);
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static void mpic_mask_irq_err(uintptr_t nb);
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static void mpic_unmask_irq_err(uintptr_t nb);
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static boolean_t mpic_irq_is_percpu(uintptr_t);
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#ifdef INTRNG
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static int mpic_intr(void *arg);
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#endif
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static void mpic_unmask_msi(void);
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void mpic_init_secondary(device_t);
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void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
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int mpic_ipi_read(int);
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void mpic_ipi_clear(int);
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#define MPIC_WRITE(softc, reg, val) \
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bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
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@ -189,7 +187,6 @@ mv_mpic_probe(device_t dev)
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return (0);
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}
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#ifdef INTRNG
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static int
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mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
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{
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@ -221,7 +218,6 @@ mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
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}
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return (0);
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}
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#endif
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static int
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mv_mpic_attach(device_t dev)
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@ -246,13 +242,11 @@ mv_mpic_attach(device_t dev)
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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#ifdef INTRNG
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if (sc->mpic_res[3] == NULL)
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device_printf(dev, "No interrupt to use.\n");
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else
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bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
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mpic_intr, NULL, sc, &sc->intr_hand);
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#endif
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sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
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sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
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@ -272,7 +266,6 @@ mv_mpic_attach(device_t dev)
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val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
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sc->nirqs = MPIC_CTRL_NIRQS(val);
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#ifdef INTRNG
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if (mv_mpic_register_isrcs(sc) != 0) {
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device_printf(dev, "could not register PIC ISRCs\n");
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bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
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@ -286,7 +279,6 @@ mv_mpic_attach(device_t dev)
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bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
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return (ENXIO);
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}
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#endif
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mpic_unmask_msi();
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@ -299,7 +291,6 @@ mv_mpic_attach(device_t dev)
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return (0);
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}
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#ifdef INTRNG
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static int
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mpic_intr(void *arg)
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{
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@ -386,20 +377,19 @@ static void
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mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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}
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#endif
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static device_method_t mv_mpic_methods[] = {
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DEVMETHOD(device_probe, mv_mpic_probe),
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DEVMETHOD(device_attach, mv_mpic_attach),
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#ifdef INTRNG
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DEVMETHOD(pic_disable_intr, mpic_disable_intr),
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DEVMETHOD(pic_enable_intr, mpic_enable_intr),
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DEVMETHOD(pic_map_intr, mpic_map_intr),
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DEVMETHOD(pic_post_filter, mpic_post_filter),
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DEVMETHOD(pic_post_ithread, mpic_post_ithread),
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DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
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#endif
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DEVMETHOD(pic_init_secondary, mpic_init_secondary),
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DEVMETHOD(pic_ipi_send, mpic_ipi_send),
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{ 0, 0 }
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};
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@ -414,46 +404,6 @@ static devclass_t mv_mpic_devclass;
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EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
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#ifndef INTRNG
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int
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arm_get_next_irq(int last)
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{
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u_int irq, next = -1;
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irq = mv_mpic_get_cause() & MPIC_IRQ_MASK;
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CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);
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if (irq != MPIC_IRQ_MASK) {
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if (irq == MPIC_INT_ERR)
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irq = mv_mpic_get_cause_err();
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if (irq == MPIC_INT_MSI)
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irq = mv_mpic_get_msi();
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next = irq;
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}
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CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
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return (next);
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}
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/*
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* XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only
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* by ISM/ICM and remove access to ICE in masking operation
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*/
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void
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arm_mask_irq(uintptr_t nb)
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{
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mpic_mask_irq(nb);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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mpic_unmask_irq(nb);
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}
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#endif
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static void
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mpic_unmask_msi(void)
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{
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@ -621,15 +571,13 @@ mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
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return (0);
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}
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#if defined(SMP) && defined(SOC_MV_ARMADAXP)
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void
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intr_pic_init_secondary(void)
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mpic_init_secondary(device_t dev)
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{
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}
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void
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pic_ipi_send(cpuset_t cpus, u_int ipi)
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mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
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{
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uint32_t val, i;
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@ -642,7 +590,7 @@ pic_ipi_send(cpuset_t cpus, u_int ipi)
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}
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int
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pic_ipi_read(int i __unused)
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mpic_ipi_read(int i __unused)
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{
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uint32_t val;
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int ipi;
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@ -658,8 +606,6 @@ pic_ipi_read(int i __unused)
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}
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void
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pic_ipi_clear(int ipi)
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mpic_ipi_clear(int ipi)
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{
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}
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#endif
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@ -54,12 +54,6 @@
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#define ENDPOINT_IRQ_MASK(n) 0x30
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#define ENDPOINT_IRQ_MASK_HI(n) 0x34
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#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
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#elif defined (SOC_MV_ARMADAXP)
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#define IRQ_CAUSE 0x18
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#define IRQ_MASK 0x30
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#elif defined (SOC_MV_ARMADA38X)
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#define MSI_IRQ 0x3ff
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#define ERR_IRQ 0x3ff
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#else
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#define IRQ_CAUSE 0x0
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#define IRQ_MASK 0x4
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@ -74,6 +68,14 @@
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#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
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#endif
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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#define ERR_IRQ (MAIN_IRQ_NUM)
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#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
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#define MSI_IRQ_NUM 32
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#define IRQ_CPU_SELF 0x00000001
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#if defined(SOC_MV_ARMADAXP)
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#define BRIDGE_IRQ_CAUSE 0x68
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#define IRQ_TIMER0 0x00000001
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